Tightly-coupled multi-layer topologies for 3-D NoCs

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

62 Citations (Scopus)

Abstract

Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length and wire delay. Although the network topology of 3-D NoC has been explored for a couple of years, there is still only a narrow range of choices. In this paper, we propose a class of 3-D topologies called Xbar-connected Network-on-Tiers (XNoTs), which consist of multiple network layers tightly connected via crossbar switches. To make the best use of the short delay and high density of inter-wafer links, XNoTs topologies have cross-bar switches that connect different layers and their cores. The planar topology on every layer can be independently customized so as to meet the cost-performance requirements, as far as network connectivity is at least guaranteed with the bottom layer. We also propose their routing algorithm, which guarantees deadlock-freedom by restricting the inter-layer packet transfer from a lower-numbered layer to a higher-numbered layer. Path sets at the bottom layer close to the heat sink of the chip can be selectively employed in order to mitigate the heat-dissipation problem of 3-D ICs. Several forms of XNoTs topologies including meshes, tori, and/or trees are created, and they are evaluated in terms of performance, cost, and energy consumption. As a result, we show that even with the flexibilities mentioned above, XNoTs achieve at least as high throughput as existing 3-D topologies for equivalent chip sizes.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
DOIs
Publication statusPublished - 2007
Event36th International Conference on Parallel Processing in Xi'an, ICPP - Xi'an, China
Duration: 2007 Sep 102007 Sep 14

Other

Other36th International Conference on Parallel Processing in Xi'an, ICPP
CountryChina
CityXi'an
Period07/9/1007/9/14

Fingerprint

Topology
Switches
Wire
Network layers
Heat sinks
Routing algorithms
Network architecture
Heat losses
Costs
Energy utilization
Throughput
Network-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture
  • Engineering(all)

Cite this

Matsutani, H., Koibuchi, M., & Amano, H. (2007). Tightly-coupled multi-layer topologies for 3-D NoCs. In Proceedings of the International Conference on Parallel Processing [4343882] https://doi.org/10.1109/ICPP.2007.79

Tightly-coupled multi-layer topologies for 3-D NoCs. / Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu.

Proceedings of the International Conference on Parallel Processing. 2007. 4343882.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsutani, H, Koibuchi, M & Amano, H 2007, Tightly-coupled multi-layer topologies for 3-D NoCs. in Proceedings of the International Conference on Parallel Processing., 4343882, 36th International Conference on Parallel Processing in Xi'an, ICPP, Xi'an, China, 07/9/10. https://doi.org/10.1109/ICPP.2007.79
Matsutani H, Koibuchi M, Amano H. Tightly-coupled multi-layer topologies for 3-D NoCs. In Proceedings of the International Conference on Parallel Processing. 2007. 4343882 https://doi.org/10.1109/ICPP.2007.79
Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu. / Tightly-coupled multi-layer topologies for 3-D NoCs. Proceedings of the International Conference on Parallel Processing. 2007.
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