Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Takao Toi, Toru Awashima, Masato Motomura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents our dynamically reconfigurable processor (DRP) and its compiler. We first introduce our DRP architecture, which is suitable for both parallelizable and control-intensive code segments since it has a stand-alone finite state machine that switches "contexts" consisting of many processing elements (PEs). Then, some optimization techniques used in the compiler are explained, such as a loop pipelining, iterative synthesis technique to shorten wire delay, and a technique to achieve higher area efficiency by utilizing the benefit of having multiple contexts. Lastly, two products are shown as application examples.

Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
DOIs
Publication statusPublished - 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: 2011 Aug 72011 Aug 10

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period11/8/711/8/10

Fingerprint

Finite automata
Switches
Wire
Processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Toi, T., Awashima, T., Motomura, M., & Amano, H. (2011). Time and space-multiplexed compilation challenges for dynamically reconfigurable processors. In Midwest Symposium on Circuits and Systems [6026300] https://doi.org/10.1109/MWSCAS.2011.6026300

Time and space-multiplexed compilation challenges for dynamically reconfigurable processors. / Toi, Takao; Awashima, Toru; Motomura, Masato; Amano, Hideharu.

Midwest Symposium on Circuits and Systems. 2011. 6026300.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Toi, T, Awashima, T, Motomura, M & Amano, H 2011, Time and space-multiplexed compilation challenges for dynamically reconfigurable processors. in Midwest Symposium on Circuits and Systems., 6026300, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 11/8/7. https://doi.org/10.1109/MWSCAS.2011.6026300
Toi, Takao ; Awashima, Toru ; Motomura, Masato ; Amano, Hideharu. / Time and space-multiplexed compilation challenges for dynamically reconfigurable processors. Midwest Symposium on Circuits and Systems. 2011.
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