Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Takao Toi, Toru Awashima, Masato Motomura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents our dynamically reconfigurable processor (DRP) and its compiler. We first introduce our DRP architecture, which is suitable for both parallelizable and control-intensive code segments since it has a stand-alone finite state machine that switches "contexts" consisting of many processing elements (PEs). Then, some optimization techniques used in the compiler are explained, such as a loop pipelining, iterative synthesis technique to shorten wire delay, and a technique to achieve higher area efficiency by utilizing the benefit of having multiple contexts. Lastly, two products are shown as application examples.

Original languageEnglish
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
Publication statusPublished - 2011 Oct 13
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: 2011 Aug 72011 Aug 10

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period11/8/711/8/10

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Toi, T., Awashima, T., Motomura, M., & Amano, H. (2011). Time and space-multiplexed compilation challenges for dynamically reconfigurable processors. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026300] (Midwest Symposium on Circuits and Systems). https://doi.org/10.1109/MWSCAS.2011.6026300