Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano

Research output: Contribution to conferencePaper

Abstract

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.

Original languageEnglish
Number of pages1
Publication statusPublished - 2005 Jun 20
EventACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States
Duration: 2005 Feb 202005 Feb 22

Conference

ConferenceACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
CountryUnited States
CityMonterey, CA
Period05/2/2005/2/22

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ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Hasegawa, Y., Abe, S., Deguchi, K., Suzuki, M., & Amano, H. (2005). Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation. Paper presented at ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States.