TORUS: Terabit-per-second ATM switching system architecture based on distributed internal speed-up ATM switch

Kouichi Genda, Naoaki Yamanaka

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A high-speed and distributed ATM switch architecture, called the TORUS switch, is proposed with the aim of achieving a terabit-per-second ATM switching system. The switch is a distributed and scalable internal speed-up crossbar-type ATM switch with cylindrical structure. The self-bit-synchronization technique and optical interconnection technology are combined to achieve gigabit-rate cell transmission, where high-density implementation technologies such as multichip module technology are not required at all. Also, distributed contention control based on the fixed output-precedence scheme is newly adopted. This control is very suitable for high-speed devices because its circuit is achieved with only one gate in each crosspoint. A TORUS switch is fabricated as a 4 × 2 switch module using optical interconnection technology and very high-speed crosspoint LSI's, constructed using an advanced Si-bipolar process. Measured results confirm that the TORUS switch can be used to realize an expandable terabit-rate ATM switch.

Original languageEnglish
Pages (from-to)817-828
Number of pages12
JournalIEEE Journal on Selected Areas in Communications
Volume15
Issue number5
DOIs
Publication statusPublished - 1997 Jun
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Networks and Communications

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