Towards the realistic `virtual hardware'

Yuichiro Shibata, Hidenori Miyazaki, Xiao Ping Ling, Hideharu Amano

Research output: Contribution to conferencePaper

Abstract

WASMII is a virtual hardware system that executes dataflow algorithms. It is based on an MPLD (Multifunction Programming Logic Device), an extended FPGA (Field Programmable Gate Array) that implements multiple sets of functions as configurations of a single chip. An algorithm to be executed on WASMII is written in the DFC dataflow language and then translated into a collection of FPGA configurations, each representing a page-sized subgraph of the dataflow graph. Although we have developed an emulation system and software environment for WASMII, it has tended to be an unrealistic system due to the difficulty of the MPLD implementation. However, with recent technologies of semiconductors, FPGA and DRAM can be implemented into a single LSI chip. By using the column buffer of the DRAM array as a configuration memory of an FPGA, replacement of configuration data can be done almost the same speed as an MPLD. Compared with the MPLD approach, a large amount of data can be stored in the integrated DRAM. Initial simulation results show that such a chip can almost save the loss caused by data transfer from the off chip memory of original WASMII.

Original languageEnglish
Pages50-55
Number of pages6
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems - Maui, HI, USA
Duration: 1997 Oct 221997 Oct 24

Other

OtherProceedings of the 1997 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
CityMaui, HI, USA
Period97/10/2297/10/24

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ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Shibata, Y., Miyazaki, H., Ling, X. P., & Amano, H. (1997). Towards the realistic `virtual hardware'. 50-55. Paper presented at Proceedings of the 1997 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Maui, HI, USA, .