Tutorial: Introduction to interconnection networks from system area network to network on chips

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Interconnection networks connect cab nets in the floors, boards in a cab net, chips on a board, and moudles inside the chip. Since protcols and network structures are not fixed unlike LAN or WAN, there are wide viriety on topologies, routing, flow control and media. As an introduction of two other tutorial sessions ('Future Low-latency Networks for High Performance Computing' and 'Research Challenges on 2-D and 3-D Network-on-Chips'), typical interconnection networks and techniques around them are explained with recent examples.

Original languageEnglish
Title of host publicationProceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013
Pages15-16
Number of pages2
DOIs
Publication statusPublished - 2013
Event2013 1st International Symposium on Computing and Networking, CANDAR 2013 - Matsuyama, Ehime, Japan
Duration: 2013 Dec 42013 Dec 6

Other

Other2013 1st International Symposium on Computing and Networking, CANDAR 2013
CountryJapan
CityMatsuyama, Ehime
Period13/12/413/12/6

Fingerprint

Wide area networks
Flow control
Local area networks
Topology
Network-on-chip

Keywords

  • Interconnection Networks

ASJC Scopus subject areas

  • Computer Networks and Communications

Cite this

Amano, H. (2013). Tutorial: Introduction to interconnection networks from system area network to network on chips. In Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013 (pp. 15-16). [6726871] https://doi.org/10.1109/CANDAR.2013.9

Tutorial : Introduction to interconnection networks from system area network to network on chips. / Amano, Hideharu.

Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. 2013. p. 15-16 6726871.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Amano, H 2013, Tutorial: Introduction to interconnection networks from system area network to network on chips. in Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013., 6726871, pp. 15-16, 2013 1st International Symposium on Computing and Networking, CANDAR 2013, Matsuyama, Ehime, Japan, 13/12/4. https://doi.org/10.1109/CANDAR.2013.9
Amano H. Tutorial: Introduction to interconnection networks from system area network to network on chips. In Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. 2013. p. 15-16. 6726871 https://doi.org/10.1109/CANDAR.2013.9
Amano, Hideharu. / Tutorial : Introduction to interconnection networks from system area network to network on chips. Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013. 2013. pp. 15-16
@inproceedings{ab6ead514720438c85e4c3b914861c15,
title = "Tutorial: Introduction to interconnection networks from system area network to network on chips",
abstract = "Interconnection networks connect cab nets in the floors, boards in a cab net, chips on a board, and moudles inside the chip. Since protcols and network structures are not fixed unlike LAN or WAN, there are wide viriety on topologies, routing, flow control and media. As an introduction of two other tutorial sessions ('Future Low-latency Networks for High Performance Computing' and 'Research Challenges on 2-D and 3-D Network-on-Chips'), typical interconnection networks and techniques around them are explained with recent examples.",
keywords = "Interconnection Networks",
author = "Hideharu Amano",
year = "2013",
doi = "10.1109/CANDAR.2013.9",
language = "English",
isbn = "9781479927951",
pages = "15--16",
booktitle = "Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013",

}

TY - GEN

T1 - Tutorial

T2 - Introduction to interconnection networks from system area network to network on chips

AU - Amano, Hideharu

PY - 2013

Y1 - 2013

N2 - Interconnection networks connect cab nets in the floors, boards in a cab net, chips on a board, and moudles inside the chip. Since protcols and network structures are not fixed unlike LAN or WAN, there are wide viriety on topologies, routing, flow control and media. As an introduction of two other tutorial sessions ('Future Low-latency Networks for High Performance Computing' and 'Research Challenges on 2-D and 3-D Network-on-Chips'), typical interconnection networks and techniques around them are explained with recent examples.

AB - Interconnection networks connect cab nets in the floors, boards in a cab net, chips on a board, and moudles inside the chip. Since protcols and network structures are not fixed unlike LAN or WAN, there are wide viriety on topologies, routing, flow control and media. As an introduction of two other tutorial sessions ('Future Low-latency Networks for High Performance Computing' and 'Research Challenges on 2-D and 3-D Network-on-Chips'), typical interconnection networks and techniques around them are explained with recent examples.

KW - Interconnection Networks

UR - http://www.scopus.com/inward/record.url?scp=84894153808&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84894153808&partnerID=8YFLogxK

U2 - 10.1109/CANDAR.2013.9

DO - 10.1109/CANDAR.2013.9

M3 - Conference contribution

AN - SCOPUS:84894153808

SN - 9781479927951

SP - 15

EP - 16

BT - Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013

ER -