Unified understanding of Vth and Id variability in tri-gate nanowire MOSFETs

M. Saitoh; K. Ota; C. Tanaka; Y. Nakabayashi; K. Uchida; T. Numata

Unified understanding of V_th and I_d variability in tri-gate nanowire MOSFETs

M. Saitoh, K. Ota, C. Tanaka, Y. Nakabayashi, K. Uchida, T. Numata

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We present the systematic study of V_th and I_dlin/ I_dsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (W_NW) and height (H_NW) down to 10nm, NW number (N_NW), NW directions, channel dopants). By adopting NW circumference as W_eff, the universal line appears in Pelgrom plot of both σV_th and σI_d for a wide range of gate length (L_g), W_NW and H_NW. We found A _vt reduction in NW Tr. compared to planar SOI Tr. due to gate grain alignment. Deviation of σV_th and σI_dlin of the narrowest Tr. from the universal line was eliminated by suppressing the parasitic resistance (R_SD). σI_dsat and σI _dlin in NW Tr. can be reduced by improving the surface-roughness- limited mobility and its variations, respectively.

Original language	English
Title of host publication	2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
Pages	132-133
Number of pages	2
Publication status	Published - 2011 Sept 16
Event	2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan Duration: 2011 Jun 15 → 2011 Jun 17

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2011 Symposium on VLSI Circuits, VLSIC 2011
Country/Territory	Japan
City	Kyoto
Period	11/6/15 → 11/6/17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Saitoh, M, Ota, K, Tanaka, C, Nakabayashi, Y, Uchida, K & Numata, T 2011, Unified understanding of V_th and I_d variability in tri-gate nanowire MOSFETs. in 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers., 5986435, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 132-133, 2011 Symposium on VLSI Circuits, VLSIC 2011, Kyoto, Japan, 11/6/15.

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abstract = "We present the systematic study of Vth and Idlin/ Idsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (WNW) and height (HNW) down to 10nm, NW number (NNW), NW directions, channel dopants). By adopting NW circumference as Weff, the universal line appears in Pelgrom plot of both σVth and σId for a wide range of gate length (Lg), WNW and HNW. We found A vt reduction in NW Tr. compared to planar SOI Tr. due to gate grain alignment. Deviation of σVth and σIdlin of the narrowest Tr. from the universal line was eliminated by suppressing the parasitic resistance (RSD). σIdsat and σI dlin in NW Tr. can be reduced by improving the surface-roughness- limited mobility and its variations, respectively.",

author = "M. Saitoh and K. Ota and C. Tanaka and Y. Nakabayashi and K. Uchida and T. Numata",

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T1 - Unified understanding of Vth and Id variability in tri-gate nanowire MOSFETs

AU - Saitoh, M.

AU - Ota, K.

AU - Tanaka, C.

AU - Nakabayashi, Y.

AU - Uchida, K.

AU - Numata, T.

PY - 2011/9/16

Y1 - 2011/9/16

N2 - We present the systematic study of Vth and Idlin/ Idsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (WNW) and height (HNW) down to 10nm, NW number (NNW), NW directions, channel dopants). By adopting NW circumference as Weff, the universal line appears in Pelgrom plot of both σVth and σId for a wide range of gate length (Lg), WNW and HNW. We found A vt reduction in NW Tr. compared to planar SOI Tr. due to gate grain alignment. Deviation of σVth and σIdlin of the narrowest Tr. from the universal line was eliminated by suppressing the parasitic resistance (RSD). σIdsat and σI dlin in NW Tr. can be reduced by improving the surface-roughness- limited mobility and its variations, respectively.

AB - We present the systematic study of Vth and Idlin/ Idsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (WNW) and height (HNW) down to 10nm, NW number (NNW), NW directions, channel dopants). By adopting NW circumference as Weff, the universal line appears in Pelgrom plot of both σVth and σId for a wide range of gate length (Lg), WNW and HNW. We found A vt reduction in NW Tr. compared to planar SOI Tr. due to gate grain alignment. Deviation of σVth and σIdlin of the narrowest Tr. from the universal line was eliminated by suppressing the parasitic resistance (RSD). σIdsat and σI dlin in NW Tr. can be reduced by improving the surface-roughness- limited mobility and its variations, respectively.

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