Unified understanding of Vth and Id variability in tri-gate nanowire MOSFETs

M. Saitoh, K. Ota, C. Tanaka, Y. Nakabayashi, K. Uchida, T. Numata

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    We present the systematic study of Vth and Idlin/ Idsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (WNW) and height (HNW) down to 10nm, NW number (NNW), NW directions, channel dopants). By adopting NW circumference as Weff, the universal line appears in Pelgrom plot of both σVth and σId for a wide range of gate length (Lg), WNW and HNW. We found A vt reduction in NW Tr. compared to planar SOI Tr. due to gate grain alignment. Deviation of σVth and σIdlin of the narrowest Tr. from the universal line was eliminated by suppressing the parasitic resistance (RSD). σIdsat and σI dlin in NW Tr. can be reduced by improving the surface-roughness- limited mobility and its variations, respectively.

    Original languageEnglish
    Title of host publication2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
    Pages132-133
    Number of pages2
    Publication statusPublished - 2011 Sep 16
    Event2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
    Duration: 2011 Jun 152011 Jun 17

    Publication series

    NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

    Other

    Other2011 Symposium on VLSI Circuits, VLSIC 2011
    CountryJapan
    CityKyoto
    Period11/6/1511/6/17

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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  • Cite this

    Saitoh, M., Ota, K., Tanaka, C., Nakabayashi, Y., Uchida, K., & Numata, T. (2011). Unified understanding of Vth and Id variability in tri-gate nanowire MOSFETs. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers (pp. 132-133). [5986435] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).