Utilizing surplus timing for power reduction

M. Hamada, Y. Ootaguro, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Citations (Scopus)

Abstract

Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
Pages89-92
Number of pages4
Publication statusPublished - 2001
EventIEEE 2001 Custom Integrated Circuits Conference - San Diego, CA, United States
Duration: 2001 May 62001 May 9

Other

OtherIEEE 2001 Custom Integrated Circuits Conference
CountryUnited States
CitySan Diego, CA
Period01/5/601/5/9

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hamada, M., Ootaguro, Y., & Kuroda, T. (2001). Utilizing surplus timing for power reduction. In Proceedings of the Custom Integrated Circuits Conference (pp. 89-92)