Utilizing surplus timing for power reduction

Mototsugu Hamada; Yukio Ootaguro; Tadahiro Kuroda

doi:10.1109/CICC.2001.929730

Utilizing surplus timing for power reduction

Mototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda

Research output: Contribution to journal › Article › peer-review

60 Citations (Scopus)

Abstract

Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.

Original language	English
Pages (from-to)	89-92
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2001.929730
Publication status	Published - 2001 Jan 1

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2001.929730

Cite this

@article{1554b2473b2b482280e810bb4576bb01,

title = "Utilizing surplus timing for power reduction",

abstract = "Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.",

author = "Mototsugu Hamada and Yukio Ootaguro and Tadahiro Kuroda",

year = "2001",

month = jan,

day = "1",

doi = "10.1109/CICC.2001.929730",

language = "English",

pages = "89--92",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Utilizing surplus timing for power reduction

AU - Hamada, Mototsugu

AU - Ootaguro, Yukio

AU - Kuroda, Tadahiro

PY - 2001/1/1

Y1 - 2001/1/1

N2 - Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.

AB - Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.

UR - http://www.scopus.com/inward/record.url?scp=0034837915&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034837915&partnerID=8YFLogxK

U2 - 10.1109/CICC.2001.929730

DO - 10.1109/CICC.2001.929730

M3 - Article

AN - SCOPUS:0034837915

SN - 0886-5930

SP - 89

EP - 92

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

ER -

Utilizing surplus timing for power reduction

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this