Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 2001 Jan 1|
ASJC Scopus subject areas
- Electrical and Electronic Engineering