Variable supply-voltage scheme for low-power high-speed CMOS digital design

Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama

Research output: Contribution to journalArticle

189 Citations (Scopus)

Abstract

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supply voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

Original languageEnglish
Pages (from-to)454-461
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume33
Issue number3
DOIs
Publication statusPublished - 1998 Mar 1
Externally publishedYes

Keywords

  • Buck converter
  • Low power CMOS circuits
  • Low threshold voltage
  • Low voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Kuroda, T., Suzuki, K., Mita, S., Fujita, T., Yamane, F., Sano, F., Chiba, A., Watanabe, Y., Matsuda, K., Maeda, T., Sakurai, T., & Furuyama, T. (1998). Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE Journal of Solid-State Circuits, 33(3), 454-461. https://doi.org/10.1109/4.661211