Vector processor design for parallel DSP systems using hierachical behavioral description based synthesizer

Hiroshi Nakada, Naoya Sakurai, Yukiharu Kanayama, Naohisa Ohta, Kiyoshi Oguri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The VLSI design of a one-chip vector processor (VP) for parallel digital signal processing (DSP) systems is described. The VP aims at a peak performance of 100 MFLOPS (32-b) for typical digital signal processing applications. To achieve this performance based on existing CMOS technology, a very-long-instruction-word-type pipeline architecture was used. The pipeline processing architecture and the functional units configuration are shown. A high-level behavioral-description-based CAD system called PARTHENON was used to design the functions and logic circuits of the VP. The suitability and effectiveness of PARTHENON for the VP design are shown in terms of parallel operation and pipeline-stage description. The estimated work load in the VP design with PARTHENON is one order of magnitude smaller compared to conventional CAD tools.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
PublisherPubl by IEEE
Pages86-89
Number of pages4
ISBN (Print)O81862079X
Publication statusPublished - 1990 Sep
EventProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA
Duration: 1990 Sep 171990 Sep 19

Other

OtherProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
CityCambridge, MA, USA
Period90/9/1790/9/19

Fingerprint

Digital signal processing
Pipelines
Computer aided design
Logic circuits
Processing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Nakada, H., Sakurai, N., Kanayama, Y., Ohta, N., & Oguri, K. (1990). Vector processor design for parallel DSP systems using hierachical behavioral description based synthesizer. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 86-89). Publ by IEEE.

Vector processor design for parallel DSP systems using hierachical behavioral description based synthesizer. / Nakada, Hiroshi; Sakurai, Naoya; Kanayama, Yukiharu; Ohta, Naohisa; Oguri, Kiyoshi.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. p. 86-89.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakada, H, Sakurai, N, Kanayama, Y, Ohta, N & Oguri, K 1990, Vector processor design for parallel DSP systems using hierachical behavioral description based synthesizer. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, pp. 86-89, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 90/9/17.
Nakada H, Sakurai N, Kanayama Y, Ohta N, Oguri K. Vector processor design for parallel DSP systems using hierachical behavioral description based synthesizer. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE. 1990. p. 86-89
Nakada, Hiroshi ; Sakurai, Naoya ; Kanayama, Yukiharu ; Ohta, Naohisa ; Oguri, Kiyoshi. / Vector processor design for parallel DSP systems using hierachical behavioral description based synthesizer. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, 1990. pp. 86-89
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