Abstract
The status of a series of numerical modelings of plasma etching processes is overviewed. Almost all models of low-temperature plasma, which were proposed in the mid- and late 1980s, are summarized, together with the boundary conditions that plasma processing faces. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/trench and electrical device damage during etching will make it possible to prepare a technology computer-aided design (CAD) for the practical purpose of prediction and designing the etching process. This system will also help to determine device arrangement and size in ultra-large-scale integrated (ULSI) circuits in a closed integration system. Our basis for this study is the vertically integrated CAD for device processing (VicAddress), which the authors recently proposed. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.
| Original language | English |
|---|---|
| Pages (from-to) | 176-200 |
| Number of pages | 25 |
| Journal | Applied Surface Science |
| Volume | 192 |
| Issue number | 1-4 |
| DOIs | |
| Publication status | Published - 2002 May 30 |
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Keywords
- Computer-aided design
- Device processing
- High aspect ratio charging
- Low temperature plasma
- Oxide etching
- Plasma structure/function
- Radio frequency plasma
- Ultra-large-scale integrated circuits
ASJC Scopus subject areas
- Physical and Theoretical Chemistry
- Surfaces, Coatings and Films
- Condensed Matter Physics
Cite this
Vertically integrated computer-aided design for device processing. / Makabe, Toshiaki; Maeshige, Kazunobu.
In: Applied Surface Science, Vol. 192, No. 1-4, 30.05.2002, p. 176-200.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Vertically integrated computer-aided design for device processing
AU - Makabe, Toshiaki
AU - Maeshige, Kazunobu
PY - 2002/5/30
Y1 - 2002/5/30
N2 - The status of a series of numerical modelings of plasma etching processes is overviewed. Almost all models of low-temperature plasma, which were proposed in the mid- and late 1980s, are summarized, together with the boundary conditions that plasma processing faces. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/trench and electrical device damage during etching will make it possible to prepare a technology computer-aided design (CAD) for the practical purpose of prediction and designing the etching process. This system will also help to determine device arrangement and size in ultra-large-scale integrated (ULSI) circuits in a closed integration system. Our basis for this study is the vertically integrated CAD for device processing (VicAddress), which the authors recently proposed. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.
AB - The status of a series of numerical modelings of plasma etching processes is overviewed. Almost all models of low-temperature plasma, which were proposed in the mid- and late 1980s, are summarized, together with the boundary conditions that plasma processing faces. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/trench and electrical device damage during etching will make it possible to prepare a technology computer-aided design (CAD) for the practical purpose of prediction and designing the etching process. This system will also help to determine device arrangement and size in ultra-large-scale integrated (ULSI) circuits in a closed integration system. Our basis for this study is the vertically integrated CAD for device processing (VicAddress), which the authors recently proposed. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.
KW - Computer-aided design
KW - Device processing
KW - High aspect ratio charging
KW - Low temperature plasma
KW - Oxide etching
KW - Plasma structure/function
KW - Radio frequency plasma
KW - Ultra-large-scale integrated circuits
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U2 - 10.1016/S0169-4332(02)00026-0
DO - 10.1016/S0169-4332(02)00026-0
M3 - Article
AN - SCOPUS:0037198349
VL - 192
SP - 176
EP - 200
JO - Applied Surface Science
JF - Applied Surface Science
SN - 0169-4332
IS - 1-4
ER -