TY - JOUR
T1 - Vertically integrated computer-aided design for device processing
AU - Makabe, Toshiaki
AU - Maeshige, Kazunobu
N1 - Funding Information:
One of the authors (TM) is grateful to his colleagues over past ten years, R. Robson, Z.Lj. Petrović, and K. Ness, and to my previous Ph.D. students, N. Shimura, N. Nakano, K. Maeda, J. Matsui. This work was partly supported by the Semiconductor Technology Academic Research Center (STARC), the Association of Super-advanced Electronics Technologies (ASET) and Semiconductor Leading Edge Technologies, Inc. (Selete).
PY - 2002/5/30
Y1 - 2002/5/30
N2 - The status of a series of numerical modelings of plasma etching processes is overviewed. Almost all models of low-temperature plasma, which were proposed in the mid- and late 1980s, are summarized, together with the boundary conditions that plasma processing faces. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/trench and electrical device damage during etching will make it possible to prepare a technology computer-aided design (CAD) for the practical purpose of prediction and designing the etching process. This system will also help to determine device arrangement and size in ultra-large-scale integrated (ULSI) circuits in a closed integration system. Our basis for this study is the vertically integrated CAD for device processing (VicAddress), which the authors recently proposed. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.
AB - The status of a series of numerical modelings of plasma etching processes is overviewed. Almost all models of low-temperature plasma, which were proposed in the mid- and late 1980s, are summarized, together with the boundary conditions that plasma processing faces. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/trench and electrical device damage during etching will make it possible to prepare a technology computer-aided design (CAD) for the practical purpose of prediction and designing the etching process. This system will also help to determine device arrangement and size in ultra-large-scale integrated (ULSI) circuits in a closed integration system. Our basis for this study is the vertically integrated CAD for device processing (VicAddress), which the authors recently proposed. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.
KW - Computer-aided design
KW - Device processing
KW - High aspect ratio charging
KW - Low temperature plasma
KW - Oxide etching
KW - Plasma structure/function
KW - Radio frequency plasma
KW - Ultra-large-scale integrated circuits
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U2 - 10.1016/S0169-4332(02)00026-0
DO - 10.1016/S0169-4332(02)00026-0
M3 - Article
AN - SCOPUS:0037198349
VL - 192
SP - 176
EP - 200
JO - Applied Surface Science
JF - Applied Surface Science
SN - 0169-4332
IS - 1-4
ER -