VIX

A router architecture for priority-aware networks-on-chip

Takuma Kogo, Nobuyuki Yamasaki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In future many-core chip multiprocessors (CMPs) and systems-on-chips (SoCs) architectures, networks-on-chip (NoC) will be one of the most critical components. In CMPs and SoCs, multiple applications will be executed concurrently and they interfere each other. Thus, packet conflicts will be caused in the NoC. Priority control is required in such environments, because each application has different bandwidth requirements and causes different traffic patterns of the packets. Unfortunately priority control degrades network performance and significantly increases the area of a priority-aware on-chip router. This paper proposes a router architecture for priority-aware NoCs in order to mitigate the performance and area overheads due to the priority control. We implement the proposed router architecture using a 90nm process technology. The synthesis result shows no critical path overhead and drastic reduction of the router area. The simulation result on a 8-ary 2-mesh network shows that the average latency of higher priority packets is reduced at the near saturation point.

Original languageEnglish
Title of host publicationProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
PublisherIEEE Computer Society
ISBN (Print)9780769543963
DOIs
Publication statusPublished - 2012
Event2010 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2010 - Hilo, HI, United States
Duration: 2010 Jan 172010 Jan 19

Other

Other2010 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2010
CountryUnited States
CityHilo, HI
Period10/1/1710/1/19

Fingerprint

Routers
Network performance
Telecommunication traffic
Microprocessor chips
Bandwidth
Network-on-chip
System-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Kogo, T., & Yamasaki, N. (2012). VIX: A router architecture for priority-aware networks-on-chip. In Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems [6685622] IEEE Computer Society. https://doi.org/10.1109/IWIA.2010.15

VIX : A router architecture for priority-aware networks-on-chip. / Kogo, Takuma; Yamasaki, Nobuyuki.

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, 2012. 6685622.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kogo, T & Yamasaki, N 2012, VIX: A router architecture for priority-aware networks-on-chip. in Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems., 6685622, IEEE Computer Society, 2010 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2010, Hilo, HI, United States, 10/1/17. https://doi.org/10.1109/IWIA.2010.15
Kogo T, Yamasaki N. VIX: A router architecture for priority-aware networks-on-chip. In Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society. 2012. 6685622 https://doi.org/10.1109/IWIA.2010.15
Kogo, Takuma ; Yamasaki, Nobuyuki. / VIX : A router architecture for priority-aware networks-on-chip. Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems. IEEE Computer Society, 2012.
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