### Abstract

Authors propose parallel/pipelined and parallel/iterative spanning tree generators for directed and undirected graphs based on graph theory algorithms using adjacency matrices. A generator employing iterative logic circuits with high regularity suitable for VLSI implementation can be realized with O(n**2) gates where n is the number of nodes in a given graph. This generator can compute a spanning tree of an nXn adjacency matrix within O(n**2) gate delays. The organizations of spanning tree generators are discussed.

Original language | English |
---|---|

Title of host publication | Proceedings - IEEE Computer Society International Conference |

Publisher | IEEE |

Pages | 401-405 |

Number of pages | 5 |

ISBN (Print) | 0818605464 |

Publication status | Published - 1984 |

Externally published | Yes |

### Fingerprint

### ASJC Scopus subject areas

- Engineering(all)

### Cite this

*Proceedings - IEEE Computer Society International Conference*(pp. 401-405). IEEE.

**VLSI SPANNING TREE GENERATORS.** / Takefuji, Yoshiyasu; Brunson, David.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings - IEEE Computer Society International Conference.*IEEE, pp. 401-405.

}

TY - GEN

T1 - VLSI SPANNING TREE GENERATORS.

AU - Takefuji, Yoshiyasu

AU - Brunson, David

PY - 1984

Y1 - 1984

N2 - Authors propose parallel/pipelined and parallel/iterative spanning tree generators for directed and undirected graphs based on graph theory algorithms using adjacency matrices. A generator employing iterative logic circuits with high regularity suitable for VLSI implementation can be realized with O(n**2) gates where n is the number of nodes in a given graph. This generator can compute a spanning tree of an nXn adjacency matrix within O(n**2) gate delays. The organizations of spanning tree generators are discussed.

AB - Authors propose parallel/pipelined and parallel/iterative spanning tree generators for directed and undirected graphs based on graph theory algorithms using adjacency matrices. A generator employing iterative logic circuits with high regularity suitable for VLSI implementation can be realized with O(n**2) gates where n is the number of nodes in a given graph. This generator can compute a spanning tree of an nXn adjacency matrix within O(n**2) gate delays. The organizations of spanning tree generators are discussed.

UR - http://www.scopus.com/inward/record.url?scp=0021579753&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0021579753&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0021579753

SN - 0818605464

SP - 401

EP - 405

BT - Proceedings - IEEE Computer Society International Conference

PB - IEEE

ER -