VLSI SPANNING TREE GENERATORS.

Yoshiyasu Takefuji, David Brunson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Authors propose parallel/pipelined and parallel/iterative spanning tree generators for directed and undirected graphs based on graph theory algorithms using adjacency matrices. A generator employing iterative logic circuits with high regularity suitable for VLSI implementation can be realized with O(n**2) gates where n is the number of nodes in a given graph. This generator can compute a spanning tree of an nXn adjacency matrix within O(n**2) gate delays. The organizations of spanning tree generators are discussed.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society International Conference
PublisherIEEE
Pages401-405
Number of pages5
ISBN (Print)0818605464
Publication statusPublished - 1984
Externally publishedYes

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Logic circuits
Graph theory

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Takefuji, Y., & Brunson, D. (1984). VLSI SPANNING TREE GENERATORS. In Proceedings - IEEE Computer Society International Conference (pp. 401-405). IEEE.

VLSI SPANNING TREE GENERATORS. / Takefuji, Yoshiyasu; Brunson, David.

Proceedings - IEEE Computer Society International Conference. IEEE, 1984. p. 401-405.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takefuji, Y & Brunson, D 1984, VLSI SPANNING TREE GENERATORS. in Proceedings - IEEE Computer Society International Conference. IEEE, pp. 401-405.
Takefuji Y, Brunson D. VLSI SPANNING TREE GENERATORS. In Proceedings - IEEE Computer Society International Conference. IEEE. 1984. p. 401-405
Takefuji, Yoshiyasu ; Brunson, David. / VLSI SPANNING TREE GENERATORS. Proceedings - IEEE Computer Society International Conference. IEEE, 1984. pp. 401-405
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