VLSI SPANNING TREE GENERATORS.

Yoshiyasu Takefuji, David Brunson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Authors propose parallel/pipelined and parallel/iterative spanning tree generators for directed and undirected graphs based on graph theory algorithms using adjacency matrices. A generator employing iterative logic circuits with high regularity suitable for VLSI implementation can be realized with O(n**2) gates where n is the number of nodes in a given graph. This generator can compute a spanning tree of an nXn adjacency matrix within O(n**2) gate delays. The organizations of spanning tree generators are discussed.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society International Conference
PublisherIEEE
Pages401-405
Number of pages5
ISBN (Print)0818605464
Publication statusPublished - 1984 Dec 1
Externally publishedYes

Publication series

NameProceedings - IEEE Computer Society International Conference

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Takefuji, Y., & Brunson, D. (1984). VLSI SPANNING TREE GENERATORS. In Proceedings - IEEE Computer Society International Conference (pp. 401-405). (Proceedings - IEEE Computer Society International Conference). IEEE.