### Abstract

Authors propose parallel/pipelined and parallel/iterative spanning tree generators for directed and undirected graphs based on graph theory algorithms using adjacency matrices. A generator employing iterative logic circuits with high regularity suitable for VLSI implementation can be realized with O(n**2) gates where n is the number of nodes in a given graph. This generator can compute a spanning tree of an nXn adjacency matrix within O(n**2) gate delays. The organizations of spanning tree generators are discussed.

Original language | English |
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Title of host publication | Proceedings - IEEE Computer Society International Conference |

Publisher | IEEE |

Pages | 401-405 |

Number of pages | 5 |

ISBN (Print) | 0818605464 |

Publication status | Published - 1984 Dec 1 |

Externally published | Yes |

### Publication series

Name | Proceedings - IEEE Computer Society International Conference |
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### ASJC Scopus subject areas

- Engineering(all)

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## Cite this

Takefuji, Y., & Brunson, D. (1984). VLSI SPANNING TREE GENERATORS. In

*Proceedings - IEEE Computer Society International Conference*(pp. 401-405). (Proceedings - IEEE Computer Society International Conference). IEEE.