Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate

Masaki Kanemoto, Masaaki Aoki, Akihiro Mochizuki, Yoshio Murakami, Mutsuharu Tsunoda, Nobuhiko Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This work clarifies the warpage and thermal stress under thermal cycling test (TCT) by 3D multi-physics solver for SiC and Si power device chip systems using direct Ag sintering chip-attachment on Cu plate. We compare the simulated warpages to the warpage results measured at room temperature for SiC/Si test structures. Measured warpages were in good agreement with our simulation values, and the simulation accuracy at Cu thickness of 1 mm was within 10 percentages for SiC structure. It was also found that the warpage in SiC structure is considerably larger than that in Si structure due to larger Young's modulus of SiC. Our simulations also showed that the warpage and displacement difference become smaller, and the thermal stress becomes stronger as the Cu plate thickness increases for both SiC/Si structures. The simulated maximum stress values under TCT decrease as Ta increases and approaches the stress free temperature. It was found that thermal stress values do not vary linearly with Ta. This nonlinearity is thought to be caused by the temperature dependence of Young's modulus of Ag sintered layer. We also clarified that the maximum stress point in the whole system is at the corner of Ag sintered bonding layer at low temperatures, and shifts to the chip center for both SiC/Si structures as Ta increases.

Original languageEnglish
Title of host publicationProceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages273-278
Number of pages6
Volume2018-May
ISBN (Print)9781538649985
DOIs
Publication statusPublished - 2018 Aug 7
Event68th IEEE Electronic Components and Technology Conference, ECTC 2018 - San Diego, United States
Duration: 2018 May 292018 Jun 1

Other

Other68th IEEE Electronic Components and Technology Conference, ECTC 2018
CountryUnited States
CitySan Diego
Period18/5/2918/6/1

Fingerprint

Thermal cycling
Thermal stress
Elastic moduli
Temperature
Sintering
Physics

Keywords

  • Ag sintering chip attachment
  • Ambient temperature dependence
  • Multi-physics solver
  • SiC/Si power devices
  • Thermal cycling test
  • Thermal stress analysis
  • Warpage

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kanemoto, M., Aoki, M., Mochizuki, A., Murakami, Y., Tsunoda, M., & Nakano, N. (2018). Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate. In Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018 (Vol. 2018-May, pp. 273-278). [8429562] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC.2018.00049

Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate. / Kanemoto, Masaki; Aoki, Masaaki; Mochizuki, Akihiro; Murakami, Yoshio; Tsunoda, Mutsuharu; Nakano, Nobuhiko.

Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Vol. 2018-May Institute of Electrical and Electronics Engineers Inc., 2018. p. 273-278 8429562.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kanemoto, M, Aoki, M, Mochizuki, A, Murakami, Y, Tsunoda, M & Nakano, N 2018, Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate. in Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. vol. 2018-May, 8429562, Institute of Electrical and Electronics Engineers Inc., pp. 273-278, 68th IEEE Electronic Components and Technology Conference, ECTC 2018, San Diego, United States, 18/5/29. https://doi.org/10.1109/ECTC.2018.00049
Kanemoto M, Aoki M, Mochizuki A, Murakami Y, Tsunoda M, Nakano N. Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate. In Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Vol. 2018-May. Institute of Electrical and Electronics Engineers Inc. 2018. p. 273-278. 8429562 https://doi.org/10.1109/ECTC.2018.00049
Kanemoto, Masaki ; Aoki, Masaaki ; Mochizuki, Akihiro ; Murakami, Yoshio ; Tsunoda, Mutsuharu ; Nakano, Nobuhiko. / Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate. Proceedings - IEEE 68th Electronic Components and Technology Conference, ECTC 2018. Vol. 2018-May Institute of Electrical and Electronics Engineers Inc., 2018. pp. 273-278
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