Wire congestion aware synthesis for a dynamically reconfigurable processor

Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.

Original languageEnglish
Title of host publicationProceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
Pages300-303
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 International Conference on Field-Programmable Technology, FPT'10 - Beijing, China
Duration: 2010 Dec 82010 Dec 10

Publication series

NameProceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

Other

Other2010 International Conference on Field-Programmable Technology, FPT'10
CountryChina
CityBeijing
Period10/12/810/12/10

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ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications

Cite this

Toi, T., Okamoto, T., Awashima, T., Wakabayashi, K., & Amano, H. (2010). Wire congestion aware synthesis for a dynamically reconfigurable processor. In Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10 (pp. 300-303). [5681481] (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10). https://doi.org/10.1109/FPT.2010.5681481