Wire congestion aware synthesis for a dynamically reconfigurable processor

Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.

Original languageEnglish
Title of host publicationProceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
Pages300-303
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 International Conference on Field-Programmable Technology, FPT'10 - Beijing, China
Duration: 2010 Dec 82010 Dec 10

Other

Other2010 International Conference on Field-Programmable Technology, FPT'10
CountryChina
CityBeijing
Period10/12/810/12/10

Fingerprint

Wire
Feedback

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Science Applications

Cite this

Toi, T., Okamoto, T., Awashima, T., Wakabayashi, K., & Amano, H. (2010). Wire congestion aware synthesis for a dynamically reconfigurable processor. In Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10 (pp. 300-303). [5681481] https://doi.org/10.1109/FPT.2010.5681481

Wire congestion aware synthesis for a dynamically reconfigurable processor. / Toi, Takao; Okamoto, Takumi; Awashima, Toru; Wakabayashi, Kazutoshi; Amano, Hideharu.

Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. 2010. p. 300-303 5681481.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Toi, T, Okamoto, T, Awashima, T, Wakabayashi, K & Amano, H 2010, Wire congestion aware synthesis for a dynamically reconfigurable processor. in Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10., 5681481, pp. 300-303, 2010 International Conference on Field-Programmable Technology, FPT'10, Beijing, China, 10/12/8. https://doi.org/10.1109/FPT.2010.5681481
Toi T, Okamoto T, Awashima T, Wakabayashi K, Amano H. Wire congestion aware synthesis for a dynamically reconfigurable processor. In Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. 2010. p. 300-303. 5681481 https://doi.org/10.1109/FPT.2010.5681481
Toi, Takao ; Okamoto, Takumi ; Awashima, Toru ; Wakabayashi, Kazutoshi ; Amano, Hideharu. / Wire congestion aware synthesis for a dynamically reconfigurable processor. Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. 2010. pp. 300-303
@inproceedings{f40bc3e939cd47f38b09e8bad9cdf102,
title = "Wire congestion aware synthesis for a dynamically reconfigurable processor",
abstract = "This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21{\%} on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.",
author = "Takao Toi and Takumi Okamoto and Toru Awashima and Kazutoshi Wakabayashi and Hideharu Amano",
year = "2010",
doi = "10.1109/FPT.2010.5681481",
language = "English",
isbn = "9781424489817",
pages = "300--303",
booktitle = "Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10",

}

TY - GEN

T1 - Wire congestion aware synthesis for a dynamically reconfigurable processor

AU - Toi, Takao

AU - Okamoto, Takumi

AU - Awashima, Toru

AU - Wakabayashi, Kazutoshi

AU - Amano, Hideharu

PY - 2010

Y1 - 2010

N2 - This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.

AB - This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.

UR - http://www.scopus.com/inward/record.url?scp=79551532395&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79551532395&partnerID=8YFLogxK

U2 - 10.1109/FPT.2010.5681481

DO - 10.1109/FPT.2010.5681481

M3 - Conference contribution

AN - SCOPUS:79551532395

SN - 9781424489817

SP - 300

EP - 303

BT - Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

ER -