XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs

H. Nakahara, Ng Anh Vu Doan, R. Yasudo, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we propose a method to design low latency and low energy networks for 3D Network-on-Chip (3D-NoC). Recent many-core processors require low-latency interconnection networks since the increasing number of cores limits the network performance. To achieve high performance in such many-core chips, small-world or random networks have been applied in the NoC field. However, the actual diameters and average shortest path lengths (ASPL) of these networks are far from the theoretical lower bound. In this work, we propose an approach based on the graph theory to design ultra low-latency topologies. We introduce a method to design a network that has low values of diameter and ASPL, with configurable upper bound of wire length, called opt ASPL. We also show that irregular topology, such as the topology used in opt ASPL, has a higher average energy consumption than general regular topology like 3D torus. In NoCs, energy budget and link length are limited, and thus such parameters must be carefully considered. Therefore, we introduce a multi-objective optimization for the ASPL and energy consumption called opt A/e which can obtain the Pareto optimal set useful for NoC designers. In a router with 64 nodes per chips and 4 chips stacked with a 3D-NoC, our proposed network optimized for energy consumption has a lower ASPL by 26.8% and a lower energy consumption by 10.9% compared to a 3D torus.

Original languageEnglish
Title of host publication2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450349840
DOIs
Publication statusPublished - 2017 Oct 19
Event11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017 - Seoul, Korea, Republic of
Duration: 2017 Oct 192017 Oct 20

Other

Other11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017
CountryKorea, Republic of
CitySeoul
Period17/10/1917/10/20

Fingerprint

Energy utilization
Topology
Graph theory
Network performance
Multiobjective optimization
Routers
Wire
Network-on-chip

Keywords

  • 3-D NoCs
  • Multi-Objective Optimization
  • Random Networks

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Nakahara, H., Doan, N. A. V., Yasudo, R., & Amano, H. (2017). XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs. In 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017 [17] Association for Computing Machinery, Inc. https://doi.org/10.1145/3130218.3130232

XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs. / Nakahara, H.; Doan, Ng Anh Vu; Yasudo, R.; Amano, Hideharu.

2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017. Association for Computing Machinery, Inc, 2017. 17.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakahara, H, Doan, NAV, Yasudo, R & Amano, H 2017, XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs. in 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017., 17, Association for Computing Machinery, Inc, 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, Seoul, Korea, Republic of, 17/10/19. https://doi.org/10.1145/3130218.3130232
Nakahara H, Doan NAV, Yasudo R, Amano H. XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs. In 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017. Association for Computing Machinery, Inc. 2017. 17 https://doi.org/10.1145/3130218.3130232
Nakahara, H. ; Doan, Ng Anh Vu ; Yasudo, R. ; Amano, Hideharu. / XYZ-Randomization using TSVs for low-latency energy efficient 3D-NoCs. 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017. Association for Computing Machinery, Inc, 2017.
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