天野 英晴

研究成果

年別の研究成果 1983 2003 2005 2007 2008 2009 2010 2011 2012 2013 2015 2016 2017 2018 2019 2020 2021 2022

• 342 Conference contribution
• 112 Article
• 21 Paper
• 14 Editorial
• 25 その他
  • 13 Conference article
  • 9 Chapter
  • 3 Review article

年別の研究成果

年別の研究成果

検索結果

• Article

  Courier: A toolchain for application acceleration on heterogeneous platforms

  Miyajima, T., Thomas, D. & Amano, H., 2015 2月 1, In: IPSJ Transactions on System LSI Design Methodology. 8, p. 105-115 11 p.

  研究成果: Article › 査読

  Open Access

  • Particle accelerators 100%
  • Spectrum analysis 33%
  • Fast Fourier transforms 31%
  • Graphics processing unit 30%
  • Image processing 25%

• Data multicasting procedure for increasing configuration speed of coarse grain reconfigurable devices

  Tunbunheng, V., Suzuki, M. & Amano, H., 2007 2月, In: IEICE Transactions on Information and Systems. E90-D, 2, p. 473-481 9 p.

  研究成果: Article › 査読

  • Multicasting 100%
  • Data storage equipment 48%
  • Clocks 34%
  1 被引用数 (Scopus)

• Design and evaluation of the cache coherent multistage interconnection network with temporary directory

  Midorikawa, T., Sumiyoshi, M., Tanabe, Y. & Amano, H., 2006 9月 1, In: Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi). 89, 9, p. 11-23 13 p.

  研究成果: Article › 査読

  • directories 100%
  • Switches 41%
  • switches 38%
  • evaluation 36%
  • entry 12%

• Design and implementation fine-grained power gating on microprocessor functional units

  Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

  研究成果: Article › 査読

  • Microprocessor chips 100%
  • Electric power utilization 40%
  3 被引用数 (Scopus)

• Design and implementation of echo instructions for an embedded processor

  Arda, K., Iver, S. & Amano, H., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 222-231 10 p.

  研究成果: Article › 査読

  • Embedded systems 100%
  • Data storage equipment 65%

• Design and implementation of reconfigurable sensing system for networked robots

  Miyajima, A., Nukata, K., Amano, H. & Anzai, Y., 1998 1月 1, In: Advanced Robotics. 13, 3, p. 253-254 2 p.

  研究成果: Article › 査読

• Design and Implementation of RHiNET-2/NI0: A Reconfigurable Network Interface for Cluster Computing

  Yokoyama, T., Izu, N., Tsuchiya, J. I., Watanabe, K., Amano, H. & Kudoh, T., 2003 5月, In: IEICE Transactions on Information and Systems. E86-D, 5, p. 789-795 7 p.

  研究成果: Article › 査読

  • Cluster computing 100%
  • Interfaces (computer) 71%
  • Data storage equipment 46%
  • Data transfer 25%
  1 被引用数 (Scopus)

• Designing High-Performance Interconnection Networks with Host-Switch Graphs

  Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2019 2月 1, In: IEEE Transactions on Parallel and Distributed Systems. 30, 2, p. 315-330 16 p., 8428449.

  研究成果: Article › 査読

  • High Performance 100%
  • Interconnection Networks 93%
  • Switch 83%
  • Switches 55%
  • Network Topology 38%
  3 被引用数 (Scopus)

• Designing low-diameter interconnection networks with multi-ported host-switch graphs

  Yasudo, R., Nakano, K., Koibuchi, M., Matsutani, H. & Amano, H., 2020, (Accepted/In press) In: Concurrency Computation Practice and Experience.

  研究成果: Article › 査読

  • Interconnection Networks 100%
  • Switch 88%
  • Switches 58%
  • Graph in graph theory 37%
  • InfiniBand 30%
  2 被引用数 (Scopus)

• Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems

  Okuhara, H., Ahmed, A. B. & Amano, H., 2018 10月, In: IEEE Transactions on Circuits and Systems I: Regular Papers. 65, 10, p. 3241-3254 14 p., 8315472.

  研究成果: Article › 査読

  • Tuning 100%
  • Electric potential 33%
  • Silicon on insulator technology 31%
  • Bias voltage 26%
  • Analog circuits 24%
  7 被引用数 (Scopus)

• Dynamic fault recovery in mesh‐connected parallel computers

  Yokota, T., Amano, H. & Aiso, H., 1986, In: Systems and Computers in Japan. 17, 7, p. 10-18 9 p.

  研究成果: Article › 査読

  • Mesh-connected Computer 100%
  • Parallel Computers 72%
  • Fault 67%
  • Recovery 57%
  • Redundancy 26%

• Dynamic power consumption optimization for inductive-coupling based wireless 3D NoCs

  Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2014 2月, In: IPSJ Transactions on System LSI Design Methodology. 7, p. 27-36 10 p.

  研究成果: Article › 査読

  • Electric power utilization 100%
  • Network-on-chip 76%
  • Telecommunication links 62%
  • System-in-package 46%
  • Topology 45%
  2 被引用数 (Scopus)

• Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

  Kagami, T., Matsutani, H., Koibuchi, M., Take, Y., Kuroda, T. & Amano, H., 2016 2月, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 2, p. 493-506 14 p., 7086053.

  研究成果: Article › 査読

  • Time division multiple access 100%
  • Carrier sense multiple access 81%
  • Network-on-chip 49%
  • Communication 44%
  • Energy transfer 25%
  16 被引用数 (Scopus)

• Environment for multiprocessor simulator development

  Wakabayashi, M. & Amano, H., 2003 10月, In: Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi). 86, 10, p. 74-84 11 p.

  研究成果: Article › 査読

  • Simulators 100%
  • Costs 29%

• Fat H-Tree: A cost-efficient tree-based on-chip network

  Matsutani, H., Koibuchi, M., Yamada, Y., Hsu, D. F. & Amano, H., 2009, In: IEEE Transactions on Parallel and Distributed Systems. 20, 8, p. 1126-1141 16 p.

  研究成果: Article › 査読

  • Network on chip 100%
  • Oils and fats 58%
  • Network-on-chip 56%
  • Costs 36%
  • Resources 10%
  21 被引用数 (Scopus)

• Fault tolerance of the TBSF (Tandem Banyan Switching Fabrics) and PBSF (Piled Banyan Switching Fabrics)

  Funahashi, A., Hanawa, T. & Amano, H., 1996 1月 1, In: IEICE Transactions on Information and Systems. E79-D, 8, p. 1180-1189 10 p.

  研究成果: Article › 査読

  • Fault tolerance 100%
  • Degradation 35%
  • Recovery 34%
  • Bandwidth 31%
  • Telecommunication links 23%

• FiC-RNN: A multi-FPGA acceleration framework for deep recurrent neural networks

  Sun, Y. & Amano, H., 2020 12月 1, In: IEICE Transactions on Information and Systems. E103D, 12, p. 2457-2462 6 p.

  研究成果: Article › 査読

  Open Access

  • Recurrent neural networks 100%
  • Deep neural networks 93%
  • Field programmable gate arrays (FPGA) 78%
  • Program processors 14%
  • Network layers 9%
  8 被引用数 (Scopus)

• Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

  Nakamura, H., Wang, W., Ohta, Y., Usami, K., Amano, H., Kondo, M. & Namiki, M., 2013 4月, In: IEICE Transactions on Electronics. E96-C, 4, p. 404-412 9 p.

  研究成果: Article › 査読

  • Software design 100%
  • Networks (circuits) 53%
  • Reduction 44%
  • Electric power utilization 42%
  • Power control 35%

• From the viewpoint of computer architecture research

  Amano, H., 2016 9月 1, In: Journal of the Institute of Electronics, Information and Communication Engineers. 99, 9, p. 907-910 4 p.

  研究成果: Article › 査読

• GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures

  Kojima, T., Doan, N. A. V. & Amano, H., 2020 11月, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 11, p. 2383-2396 14 p., 9149647.

  研究成果: Article › 査読

  • Reconfigurable architectures 100%
  • Energy efficiency 17%
  • Edge computing 13%
  • Multiobjective optimization 10%
  • Embedded systems 10%
  4 被引用数 (Scopus)

• Hierarchical multistage interconnection network R-Clos

  Morimura, T., Iwai, K. & Amano, H., 2006 11月 1, In: Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi). 89, 11, p. 30-39 10 p.

  研究成果: Article › 査読

  • Stochastic models 100%
  • Communication 91%
  • Large scale systems 78%
  • Throughput 63%
  • Bandwidth 57%
  2 被引用数 (Scopus)

• High-speed fully-adaptable CRC accelerators

  Akagic, A. & Amano, H., 2013 6月, In: IEICE Transactions on Information and Systems. E96-D, 6, p. 1299-1308 10 p.

  研究成果: Article › 査読

  • Particle accelerators 100%
  • Redundancy 83%
  • Computer hardware 21%
  • Field programmable gate arrays (FPGA) 20%
  • Shift registers 15%
  1 被引用数 (Scopus)

• Implementation of Data Driven Applications on a Multi-Context Reconfigurable Device

  Uno, M., Shibata, Y. & Amano, H., 2003 5月, In: IEICE Transactions on Information and Systems. E86-D, 5, p. 841-849 9 p.

  研究成果: Article › 査読

  • Program processors 100%
  • Computer hardware 69%

• Improving the performance of circuit-switched interconnection network for a multi-FPGA system

  Ito, K., Iizuka, K., Hironaka, K., Hu, Y., Koibuchi, M. & Amano, H., 2021, In: IEICE Transactions on Information and Systems. E104D, 12, p. 2029-2039 11 p.

  研究成果: Article › 査読

  Open Access

  • Switching networks 100%
  • Time division multiplexing 93%
  • Field programmable gate arrays (FPGA) 71%
  • Switches 63%
  • Networks (circuits) 48%
  2 被引用数 (Scopus)

• Iterative synthesis methods estimating programmable-wire congestion in a dynamically reconfigurable processor

  Toi, T., Okamoto, T., Awashima, T., Wakabayashi, K. & Amano, H., 2011 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2619-2627 9 p.

  研究成果: Article › 査読

  • Congestion 100%
  • Synthesis 69%
  • Wire 58%
  • Critical Path 20%
  • Scheduler 18%

• Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning

  Kojima, T., Ohwada, A. & Amano, H., 2022 5月 1, In: IEEE Transactions on Parallel and Distributed Systems. 33, 5, p. 1213-1230 18 p.

  研究成果: Article › 査読

  • Reconfigurable Architectures 100%
  • Reconfigurable architectures 62%
  • Partitioning 46%
  • Learning 42%
  • Deep learning 42%

• Martini: A network interface controller chip for high performance computing with distributed PCs

  Watanabe, K., Otsuka, T., Tsuchiya, J., Nishi, H., Yamamoto, J., Tanabe, N., Kudoh, T. & Amano, H., 2007 9月, In: IEEE Transactions on Parallel and Distributed Systems. 18, 9, p. 1282-1295 14 p.

  研究成果: Article › 査読

  • High Performance Computing 100%
  • Chip 82%
  • Distributed computer systems 67%
  • Controller 61%
  • Interfaces (computer) 60%
  6 被引用数 (Scopus)

• MINC: Multistage interconnection network with cache control mechanism

  Hanawa, T., Kamei, T., Yasukawa, H., Nishimura, K., Amano, H. & Tsudat, N., 1997 1月 1, In: IEICE Transactions on Information and Systems. E80-D, 9, p. 863-870 8 p.

  研究成果: Article › 査読

  • Broadcasting 100%
  • Multicasting 60%
  • Coloring 57%
  • Networks (circuits) 53%
  • Parallel processing systems 49%
  4 被引用数 (Scopus)

• MMLRU selection function: A simple and efficient output selection function in adaptive routing

  Koibuchi, M., Jouraku, A. & Amano, H., 2005 1月, In: IEICE Transactions on Information and Systems. E88-D, 1, p. 109-118 10 p.

  研究成果: Article › 査読

  • Routing algorithms 100%
  • Adaptive algorithms 98%
  • Routers 47%
  • Throughput 34%
  • Topology 33%
  4 被引用数 (Scopus)

• Multi-voltage variable pipeline routers with the same clock frequency for low-power network-on-chips systems

  Ahmed, A. B., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2016 8月 1, In: IEICE Transactions on Electronics. E99C, 8, p. 909-917 9 p.

  研究成果: Article › 査読

  • Pipeline 100%
  • Network-on-chip 96%
  • Routers 82%
  • Clocks 73%
  • Pipelines 65%
  2 被引用数 (Scopus)

• NCC: A concurrent description language for scientific calculation on multiprocessors

  Boku, T., Kudoh, T., Amano, H. & Kimura, T., 1991, In: Systems and Computers in Japan. 22, 12, p. 1-10 10 p.

  研究成果: Article › 査読

  • Multiprocessor 100%
  • Concurrent 82%
  • Language 54%
  • Process Model 27%
  • Model 8%

• Neural network parallel computing for multi-layer channel routing problems

  Suzuki, K., Amano, H. & Takefuji, Y., 1995 7月, In: Neurocomputing. 8, 2, p. 141-156 16 p.

  研究成果: Article › 査読

  • Parallel processing systems 100%
  • Neural networks 59%
  • Polychlorinated Biphenyls 41%
  • Electrical engineering 37%
  • Polychlorinated biphenyls 35%
  1 被引用数 (Scopus)

• Novel chip stacking methods to extend both horizontally and vertically for many-core architectures with ThrouChip interface

  Nakahara, H., Ozaki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2016 12月, In: IEICE Transactions on Information and Systems. E99D, 12, p. 2871-2880 10 p.

  研究成果: Article › 査読

  • System-on-chip 100%
  • Masks 92%
  • Large scale systems 83%
  • Costs 74%
  2 被引用数 (Scopus)

• Optimization of body biasing for variable pipelined coarse-grained reconfigurable architectures

  Kojima, T., Ando, N., Okuhara, H., Doan, N. A. V. & Amano, H., 2018 6月, In: IEICE Transactions on Information and Systems. E101D, 6, p. 1532-1540 9 p.

  研究成果: Article › 査読

  • Reconfigurable architectures 100%
  • Pipelines 57%
  • Bias voltage 26%
  • Silicon 16%
  • Oxides 9%
  2 被引用数 (Scopus)

• Partial reconfiguration of flux limiter functions in MUSCL scheme using FPGA

  Abu Talip, M. S., Akamine, T., Osana, Y., Fujita, N. & Amano, H., 2012 10月, In: IEICE Transactions on Information and Systems. E95-D, 10, p. 2369-2376 8 p.

  研究成果: Article › 査読

  • Limiters 100%
  • Field programmable gate arrays (FPGA) 67%
  • Fluxes 66%
  • Computational fluid dynamics 30%
  • Aerospace industry 22%

• Path selection algorithm: The strategy for designing deterministic routing from alternative paths

  Koibuchi, M., Jouraku, A. & Amano, H., 2005 1月, In: Parallel Computing. 31, 1, p. 117-130 14 p.

  研究成果: Article › 査読

  • Routing 100%
  • Strategy 64%
  • Path 62%
  • Alternatives 56%
  • Virtual Channel 37%
  4 被引用数 (Scopus)

• Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

  Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 4月, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

  研究成果: Article › 査読

  • Routers 100%
  • Network-on-chip 19%
  • Application programs 15%
  • Communication 8%
  33 被引用数 (Scopus)

• Performance analysis of parallel machines using multi‐read memory

  Amano, H., Chikawa, J., Yoshida, T. & Also, H., 1985, In: Systems and Computers in Japan. 16, 3, p. 29-37 9 p.

  研究成果: Article › 査読

  • Parallel Machines 100%
  • Performance Analysis 95%
  • Markov chains 49%
  • Markov Chain Model 48%
  • Data storage equipment 46%

• Performance evaluation of deterministic routings, multicasts, and topologies on RHiNET-2 cluster

  Koibuchi, M., Watanabe, K., Otsuka, T. & Amano, H., 2005 8月, In: IEEE Transactions on Parallel and Distributed Systems. 16, 8, p. 747-759 13 p.

  研究成果: Article › 査読

  • Multicast Routing 100%
  • Performance Evaluation 73%
  • Routing 60%
  • Percent 53%
  • PC Cluster 41%
  7 被引用数 (Scopus)

• Performance Evaluation of Instruction Set Architecture of MBP-Light in JUMP-1

  Suzuki, N. & Amano, H., 2003 10月, In: IEICE Transactions on Information and Systems. E86-D, 10, p. 1996-2005 10 p.

  研究成果: Article › 査読

  • Data storage equipment 100%
  • Reduced instruction set computing 68%

• Performance evaluation of SNAIL: A multiprocessor based on the Simple Serial Synchronized Multistage Interconnection Network architecture

  Yamamoto, J., Fujiwara, T., Komeda, T., Kamei, T., Hanawa, T. & Amano, H., 1999 9月, In: Parallel Computing. 25, 9, p. 1081-1103 23 p.

  研究成果: Article › 査読

  • Multistage Interconnection Networks 100%
  • Network Architecture 86%
  • Multiprocessor 76%
  • Performance Evaluation 75%
  • Network architecture 53%
  4 被引用数 (Scopus)

• Pot: A General Purpose Monitor for Parallel Computers

  Kanamori, Y., Minabe, O., Wakabayashi, M. & Amano, H., 2003 10月, In: IEICE Transactions on Information and Systems. E86-D, 10, p. 2025-2033 9 p.

  研究成果: Article › 査読

  • Parallel architectures 100%
  • Computer program listings 79%
  • Monitoring 48%
  • Communication 43%
  • Costs 32%

• Power Optimization Methodology for Ultralow Power Microcontroller with Silicon on Thin BOX MOSFET

  Okuhara, H., Fujita, Y., Usami, K. & Amano, H., 2017 4月, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 4, p. 1578-1582 5 p., 7802624.

  研究成果: Article › 査読

  • Microcontrollers 100%
  • Silicon 80%
  • Bias voltage 42%
  • Temperature 41%
  • Electric potential 17%
  15 被引用数 (Scopus)

• Prediction router: A low-latency on-chip router architecture with multiple predictors

  Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2011, In: IEEE Transactions on Computers. 60, 6, p. 783-799 17 p., 5703069.

  研究成果: Article › 査読

  • Router 100%
  • Latency 87%
  • Chip 85%
  • Architecture 74%
  • Routers 64%
  21 被引用数 (Scopus)

• Proxy responses by FPGA-based switch for MapReduce stragglers

  Mitsuzuka, K., Koibuchi, M., Amano, H. & Matsutani, H., 2018 9月, In: IEICE Transactions on Information and Systems. E101D, 9, p. 2258-2268 11 p.

  研究成果: Article › 査読

  • Field programmable gate arrays (FPGA) 100%
  • Switches 87%
  • Ethernet 50%
  • Communication 12%
  • Experiments 8%
  2 被引用数 (Scopus)

• pSAS/c: Pseudo Set Associative and Shared with Competitive Cache

  Inoue, K. & Amano, H., 2003 9月, In: Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi). 86, 9, p. 76-84 9 p.

  研究成果: Article › 査読

  • Cache memory 100%
  • Copying 98%
  • chips 61%
  • Costs 29%
  • central processing units 26%

• Reconfigurable out-of-order system for fluid dynamics computation using unstructured mesh

  Akamine, T., Abu Talip, M. S., Osana, Y., Fujita, N. & Amano, H., 2014 5月, In: IEICE Transactions on Information and Systems. E96-D, 5, p. 1225-1234 10 p.

  研究成果: Article › 査読

  • Fluid dynamics 100%
  • Aerodynamics 75%
  • Subroutines 42%
  • Hazards 33%
  • Computational fluid dynamics 28%
  1 被引用数 (Scopus)

• Recovering faulty non-volatile flip flops for coarse-grained reconfigurable architectures

  IKEZOE, T., KOJIMA, T. & AMANO, H., 2021 6月 1, In: IEICE Transactions on Electronics. 1, 6, p. 215-225 11 p.

  研究成果: Article › 査読

  • Reconfigurable architectures 100%
  • Flip flop circuits 88%
  • Data storage equipment 45%
  • Availability 32%
  • Time 27%

• ReCSiP: An FPGA-based general-purpose biochemical simulator

  Osana, Y., Yoshimi, M., Iwaoka, Y., Kojima, T., Nishikawa, Y., Funahashi, A., Hiroi, N., Shibata, Y., Iwanaga, N., Kitano, H. & Amano, H., 2007 7月 1, In: Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi). 90, 7, p. 1-10 10 p.

  研究成果: Article › 査読

  • simulators 100%
  • Microprocessor chips 91%
  • Field programmable gate arrays (FPGA) 83%
  • Scanning 78%
  • Simulators 73%
  10 被引用数 (Scopus)

• Recursive diagonal torus: An interconnection network for massively parallel computers

  Yang, Y., Funahashi, A., Jouraku, A., Nishi, H., Amano, H. & Sueyoshi, T., 2001 7月, In: IEEE Transactions on Parallel and Distributed Systems. 12, 7, p. 701-715 15 p.

  研究成果: Article › 査読

  • BiCMOS technology 100%
  • Multicasting 96%
  • Parallel Computers 95%
  • Interconnection Networks 94%
  • Routing algorithms 78%
  56 被引用数 (Scopus)