英晴 天野 の写真なし

Scopus著者プロファイル

天野 英晴

Pureの文献数とScopusの被引用数に基づいて算出されます
1983 …2022

年別の研究成果

Pureに変更を加えた場合、すぐここに表示されます。
フィルター
Conference contribution

検索結果

  • 2010

    A deadlock-free non-minimal fully adaptive routing using virtual cut-through switching

    Nishikawa, Y., Koibuchi, M., Matsutani, H. & Amano, H., 2010 10月 27, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 431-438 8 p. 5575700. (Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010).

    研究成果: Conference contribution

    1 被引用数 (Scopus)

  • A low-power fault-tolerant noc using error correction and detection codes

    Kojima, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010 1月 1, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 111-118 8 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    研究成果: Conference contribution

    1 被引用数 (Scopus)

  • A performance evaluation of CUBE: One-dimensional 512 FPGA cluster

    Yoshimi, M., Nishikawa, Y., Miki, M., Hiroyasu, T., Amano, H. & Mencer, O., 2010, Reconfigurable Computing: Architectures, Tools and Applications - 6th International Symposium, ARC 2010, Proceedings. p. 372-381 10 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 5992 LNCS).

    研究成果: Conference contribution

    6 被引用数 (Scopus)

  • A proposal of thread virtualization environment for cell broadband engine

    Yamada, M., Nishikawa, Y., Yoshimi, M. & Amano, H., 2010, Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2010. p. 32-39 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    研究成果: Conference contribution

    2 被引用数 (Scopus)

  • A variable-pipeline on-chip router optimized to traffic pattern

    Hirata, Y., Matsutani, H., Koibuchi, M. & Amano, H., 2010, 3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43. p. 57-62 6 p. (3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43).

    研究成果: Conference contribution

    7 被引用数 (Scopus)

  • Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

    Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 369-370 2 p. 5419857. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    研究成果: Conference contribution

    5 被引用数 (Scopus)

  • MuCCRA-3: A low power dynamically reconfigurable processor array

    Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y., Kimura, M. & Amano, H., 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 377-378 2 p. 5419853. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    研究成果: Conference contribution

    5 被引用数 (Scopus)

  • Performance, cost, and power evaluations of on-chip network topologies in FPGAs

    In, S., Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2010 7月 20, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. p. 181-189 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    研究成果: Conference contribution

  • Preliminary evaluation of batch-learning self-organizing map algorithm on a graphic processor

    Shitara, A., Nishikawa, Y., Yoshimi, M., Abe, T., Ikemura, T. & Amano, H., 2010, Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010. Acta Press, p. 96-104 9 p. (Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010).

    研究成果: Conference contribution

  • Reducing instruction TLB's leakage power consumption for embedded processors

    Lei, Z., Xu, H., Ikebuchi, D., Amano, H., Sunata, T. & Namiki, M., 2010, 2010 International Conference on Green Computing, Green Comp 2010. IEEE Computer Society, p. 477-484 8 p. 5598277. (2010 International Conference on Green Computing, Green Comp 2010).

    研究成果: Conference contribution

    2 被引用数 (Scopus)

  • Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

    Hironaka, K., Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2010 12月 1, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 349-352 4 p. 5681431. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

    研究成果: Conference contribution

    1 被引用数 (Scopus)

  • Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks

    Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2010, Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010. p. 218-227 10 p. 5575649. (Proceedings - 2010 IEEE International Conference on Networking, Architecture and Storage, NAS 2010).

    研究成果: Conference contribution

  • Ultra fine-grained run-time power gating of on-chip routers for CMPs

    Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560. (NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip).

    研究成果: Conference contribution

    60 被引用数 (Scopus)

  • Wire congestion aware synthesis for a dynamically reconfigurable processor

    Toi, T., Okamoto, T., Awashima, T., Wakabayashi, K. & Amano, H., 2010 12月 1, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. p. 300-303 4 p. 5681481. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

    研究成果: Conference contribution

    4 被引用数 (Scopus)
  • 2009

    A modular approach to heterogeneous biochemical model simulation on an FPGA

    Yamada, H., Osana, Y., Ishimori, T., Ooya, T., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2009 12月 1, ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs. p. 125-130 6 p. 5382039. (ReConFig'09 - 2009 International Conference on ReConFigurable Computing and FPGAs).

    研究成果: Conference contribution

    1 被引用数 (Scopus)

  • An on/off link activation method for low-power ethernet in PC clusters

    Koibuchi, M., Otsuka, T., Matsutani, H. & Amano, H., 2009, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161069. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

    研究成果: Conference contribution

    13 被引用数 (Scopus)

  • A scalable 3D processor by homogeneous chip stacking with inductive-coupling link

    Kohama, Y., Sugimori, Y., Saito, S., Hasegawa, Y., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Amano, H. & Kuroda, T., 2009 11月 18, 2009 Symposium on VLSI Circuits. p. 94-95 2 p. 5205288. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

    研究成果: Conference contribution

    15 被引用数 (Scopus)

  • A study on interconnection networks of the dynamically reconfigurable processor array MuCCRA

    Kato, M., Sano, T., Yasuda, Y., Saito, Y. & Amano, H., 2009 12月 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 415-418 4 p. 5377694. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

    研究成果: Conference contribution

    2 被引用数 (Scopus)

  • Balanced dimension-order routing for k-ary n-cubes

    Montañana, J. M., Koibuchi, M., Matsutani, H. & Amano, H., 2009, ICPPW 2009 - The 38th International Conference Parallel Processing Workshops. p. 499-506 8 p. 5365405. (Proceedings of the International Conference on Parallel Processing Workshops).

    研究成果: Conference contribution

    13 被引用数 (Scopus)

  • Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator

    Ooya, T., Yamada, H., Ishimori, T., Shibata, Y., Osana, Y., Oguri, K., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N. & Amano, H., 2009 11月 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 679-682 4 p. 5272335. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

    研究成果: Conference contribution

    2 被引用数 (Scopus)

  • Design and implementation of fine-grain power gating with ground bounce suppression

    Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703. (Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems).

    研究成果: Conference contribution

    30 被引用数 (Scopus)

  • Embedded software compression with split echo instructions

    Stubdal, I., Karaduman, A. & Amano, H., 2009 10月 27, 2009 IEEE 13th International Symposium on Consumer Electronics, ISCE 2009. p. 816-818 3 p. 5157058. (Digest of Technical Papers - IEEE International Conference on Consumer Electronics).

    研究成果: Conference contribution

    1 被引用数 (Scopus)

  • Evaluation of a multicore reconfigurable architecture with variable core sizes

    Tuan, V. M., Katsura, N., Matsutani, H. & Amano, H., 2009 11月 25, IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium. 5161225. (IPDPS 2009 - Proceedings of the 2009 IEEE International Parallel and Distributed Processing Symposium).

    研究成果: Conference contribution

    4 被引用数 (Scopus)

  • Fine grain partial reconfiguration for energy saving in dynamically reconfigurable processors

    Sano, T., Saito, Y., Kato, M. & Amano, H., 2009 11月 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 530-533 4 p. 5272435. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

    研究成果: Conference contribution

    2 被引用数 (Scopus)

  • Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

    Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009 12月 1, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

    研究成果: Conference contribution

    33 被引用数 (Scopus)

  • Implementation and evaluation of fine-grain run-time power gating for a multiplier

    Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009 12月 1, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

    研究成果: Conference contribution

    7 被引用数 (Scopus)

  • Implementation and evaluation of self-organizing map algorithm on a graphic processor

    Shitara, A., Nishikawa, Y., Yoshimi, M. & Amano, H., 2009 12月 1, Proceedings of the 21st IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2009. p. 253-260 8 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    研究成果: Conference contribution

    2 被引用数 (Scopus)

  • Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using dual Vt cells

    Hirai, K., Kato, M., Saito, Y. & Amano, H., 2009, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 104-111 8 p. 5377641. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

    研究成果: Conference contribution

    7 被引用数 (Scopus)

  • Low power image processing using MuCCRA-3: A dynamically reconfigurable processor array

    Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y. & Amano, H., 2009 12月 1, Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09. p. 364-367 4 p. 5377614. (Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09).

    研究成果: Conference contribution

    2 被引用数 (Scopus)

  • Modularizing flux limiter functions for a computational fluid dynamics accelerator on FPGAS

    Inakagata, K., Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2009 11月 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 654-657 4 p. 5272347. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

    研究成果: Conference contribution

    7 被引用数 (Scopus)

  • MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

    Saito, S., Kohama, Y., Sugimori, Y., Hasegawa, Y., Matsutani, H., Sano, T., Kasuga, K., Yoshida, Y., Niitsu, K., Miura, N., Kuroda, T. & Amano, H., 2009 11月 25, FPL 09: 19th International Conference on Field Programmable Logic and Applications. p. 6-11 6 p. 5272565. (FPL 09: 19th International Conference on Field Programmable Logic and Applications).

    研究成果: Conference contribution

    22 被引用数 (Scopus)

  • Performance analysis of clearspeed's CSX600 interconnects

    Nishikawa, Y., Koibuchi, M., Yoshimi, M., Shitara, A., Miura, K. & Amano, H., 2009 11月 19, Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009. p. 203-210 8 p. 5207934. (Proceedings - 2009 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009).

    研究成果: Conference contribution

    1 被引用数 (Scopus)

  • Prediction router: Yet another low latency on-chip router architecture

    Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2009, Proceedings - 15th International Symposium on High-Performance Computer Architecture, HPCA - 15 2009. IEEE Computer Society, p. 367-378 12 p. 4798274. (Proceedings - International Symposium on High-Performance Computer Architecture).

    研究成果: Conference contribution

    71 被引用数 (Scopus)
  • 2008

    Adding slow-silent virtual channels for low-power on-chip networks

    Matsutani, H., Koibuchi, M., Wang, D. & Amano, H., 2008, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 23-32 10 p. 4492722. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

    研究成果: Conference contribution

    38 被引用数 (Scopus)

  • A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

    Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924. (26th IEEE International Conference on Computer Design 2008, ICCD).

    研究成果: Conference contribution

    36 被引用数 (Scopus)

  • A lightweight fault-tolerant mechanism for network-on-chip

    Koibuchi, M., Matsutani, H., Amano, H. & Pinkston, T. M., 2008 5月 28, Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008. p. 13-22 10 p. 4492721. (Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008).

    研究成果: Conference contribution

    117 被引用数 (Scopus)

  • A method for capturing state data on dynamically reconfigurable processors

    Tuan, V. M. & Amano, H., 2008, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 208-214 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

    研究成果: Conference contribution

    1 被引用数 (Scopus)

  • A preemption algorithm for a multitasking environment on dynamically reconfigurable processor

    Tuan, V. M. & Amano, H., 2008 9月 22, Reconfigurable Computing: Architectures, Tools and Applications - 4th International Workshop, ARC 2008, Proceedings. p. 172-184 13 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4943 LNCS).

    研究成果: Conference contribution

  • Design and implementation of adaptive Viterbi decoder for using a dynamic reconfigurable processor

    Kishimoto, Y., Haruyama, S. & Amano, H., 2008 12月 1, Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008. p. 247-252 6 p. 4731802. (Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008).

    研究成果: Conference contribution

    6 被引用数 (Scopus)

  • ESPRIT/sim: A high speed performance-simulator for heterogeneous embedded multiprocessors

    Ohmiya, Y. & Amano, H., 2008 12月 1, Proceedings of the 20th IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2008. p. 252-257 6 p. (Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems).

    研究成果: Conference contribution

  • Evaluation of MuCCRA-D: A dynamically reconfigurable processor with directly interconnected PEs

    Kato, M., Hasegawa, Y. & Amano, H., 2008 12月 1, Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. p. 215-221 7 p. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

    研究成果: Conference contribution

    3 被引用数 (Scopus)

  • Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

    Morishita, H., Osana, Y., Fujita, N. & Amano, H., 2008 12月 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 193-200 8 p. 4762383. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

    研究成果: Conference contribution

    12 被引用数 (Scopus)

  • Exploring the optimal size for multicasting configuration data of dynamically Reconfigurable processors

    Nakamura, T., Sano, T., Hasegawa, Y., Tsutsumi, S., Tunbunheng, V. & Amano, H., 2008 12月 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 137-144 8 p. 4762376. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

    研究成果: Conference contribution

    3 被引用数 (Scopus)

  • Implementation and evaluation of the mechanisms for low latency communication on DIMMnet-2

    Miyabe, Y., Kitamura, A., Hamada, Y., Miyasiro, T., Izawa, T., Tanabe, N., Nakajo, H. & Amano, H., 2008, High-Performance Computing - 6th International Symposium, ISHPC 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers. Springer Verlag, p. 211-218 8 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 4759 LNCS).

    研究成果: Conference contribution

  • Instruction buffer mode for multi-context dynamically reconfigurable processors

    Sano, T., Kato, M., Tsutsumi, S., Hasegawa, Y. & Amano, H., 2008 11月 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 215-220 6 p. 4629934. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

    研究成果: Conference contribution

    4 被引用数 (Scopus)

  • Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

    Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

    研究成果: Conference contribution

    15 被引用数 (Scopus)

  • Power reduction techniques for dynamically reconfigurable processor arrays

    Nishimura, T., Hirai, K., Saito, Y., Nakamura, T., Hasegawa, Y., Tsutsusmi, S., Tunbunheng, V. & Amano, H., 2008 11月 3, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 305-310 6 p. 4629949. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

    研究成果: Conference contribution

    18 被引用数 (Scopus)

  • Practical implementation of a network-based Stochastic biochemical simulation system on an FPGA

    Yoshimi, M., Nishikawa, Y., Osana, Y., Funahashi, A., Hiroi, N., Shibata, Y., Yamada, H., Kitano, H. & Amano, H., 2008, Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL. p. 663-666 4 p. 4630034. (Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL).

    研究成果: Conference contribution

    5 被引用数 (Scopus)

  • Run-time power gating of on-chip routers using look-ahead routing

    Matsutani, H., Koibuchi, M., Amano, H. & Wang, D., 2008, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC. p. 55-60 6 p. 4484015. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

    研究成果: Conference contribution

    75 被引用数 (Scopus)

  • Three-dimensional layout of on-chip tree-based networks

    Matsutani, H., Koibuchi, M., Hsu, D. F. & Amano, H., 2008, Proceedings - 9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008. p. 281-288 8 p. 4520228. (Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN).

    研究成果: Conference contribution

    12 被引用数 (Scopus)