• 2575 引用
  • 23 h指数
1983 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

フィルター
Paper
2014

Task level pipelining on multiple accelerators via FPGA switch

Miyajima, T., Kuhara, T., Hanawa, T., Amano, H. & Boku, T., 2014 1 1, p. 267-274. 8 p.

研究成果: Paper

2013
4 引用 (Scopus)

A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

Tsusaka, A., Izawa, M., Uno, R., Ozaki, N. & Amano, H., 2013 1 1.

研究成果: Paper

1 引用 (Scopus)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

Koizumi, Y., Miura, N., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 1 1.

研究成果: Paper

2012

An OpenCL runtime library for embedded multi-core accelerator

Sakamoto, R., Sato, M., Koizumi, Y., Amano, H. & Namiki, M., 2012 11 19, p. 419-422. 4 p.

研究成果: Paper

1 引用 (Scopus)

Fine-grained power control using a multi-voltage variable pipeline router

Nakamura, T., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2012 12 1, p. 59-66. 8 p.

研究成果: Paper

4 引用 (Scopus)

Removing context memory from a multi-context dynamically reconfigurable processor

Amano, H., Kimura, M. & Ozaki, N., 2012 12 1, p. 92-99. 8 p.

研究成果: Paper

6 引用 (Scopus)
2005

Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Hasegawa, Y., Abe, S., Deguchi, K., Suzuki, M. & Amano, H., 2005 6 20. 1 p.

研究成果: Paper

2004

A new memory module for COTS-based personal supercomputing

Tanabe, N., Nakatake, M., Hakozaki, H., Dohi, Y., Nakajo, H. & Amano, H., 2004 12 1, p. 40-48. 9 p.

研究成果: Paper

11 引用 (Scopus)

ReCSiP: A ReConfigurable cell simulation platform - Accelerating biological applications with FPGA

Osana, Y., Fukushima, T. & Amano, H., 2004 6 1, p. 731-733. 3 p.

研究成果: Paper

5 引用 (Scopus)
1998

MINC (Multistage Interconnection Network with Cache control mechanism) chip

Midorikawa, T., Kamei, T., Hanawa, T. & Amano, H., 1998 12 1, p. 337-338. 2 p.

研究成果: Paper

2 引用 (Scopus)

Reconfigurable systems: Activities in Asia and South Pacific

Amano, H. & Shibata, Y., 1998 12 1, p. 453-457. 5 p.

研究成果: Paper

4 引用 (Scopus)
1997

LSI implementation of the simple serial synchronized multistage interconnection network

Kamei, T., Sasahara, M. & Amano, H., 1997 1 1, p. 673-674. 2 p.

研究成果: Paper

1 引用 (Scopus)

Memory based light weight communication architecture for local area distributed computing

Kudoh, T., Yamamoto, J., Sudoh, F., Amano, H., Ishikawa, Y. & Sato, M., 1997 12 1, p. 133-139. 7 p.

研究成果: Paper

5 引用 (Scopus)

RDT network router chip

Nishi, H., Amano, H., Nishimura, K., Anjo, K. I. & Kudoh, T., 1997 1 1, p. 675-676. 2 p.

研究成果: Paper

Towards the realistic `virtual hardware'

Shibata, Y., Miyazaki, H., Ling, X. P. & Amano, H., 1997 12 1, p. 50-55. 6 p.

研究成果: Paper

Wavelength division multiple access ring: Virtual topology on a simple ring network

Dong, X., Kudoh, T. & Amano, H., 1997 1 1, p. 30-36. 7 p.

研究成果: Paper

1 引用 (Scopus)
1996

Distributed shared memory architecture for JUMP-1: A general-purpose MPP prototype

Matsumoto, T., Kudoh, T., Nishimura, K., Hiraki, K., Amano, H. & Tanaka, H., 1996 1 1, p. 131-137. 7 p.

研究成果: Paper

5 引用 (Scopus)
1995
1994

Message transfer algorithms on the recursive diagonal torus

Yang, Y. & Amano, H., 1994 12 1, p. 310-317. 8 p.

研究成果: Paper

4 引用 (Scopus)

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations

Hiraki, K., Amano, H., Kuga, M., Sueyoshi, T., Kudoh, T., Nakashima, H., Nakajo, H., Matsuda, H., Matsumoto, T. & Mori, S. I., 1994 12 1, p. 427-434. 8 p.

研究成果: Paper

10 引用 (Scopus)