• 2574 引用
  • 23 h指数
1983 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

フィルター
Article

(SM)2-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations

Amano, H., Boku, T. & Kudoh, T., 1990 7, : : IEEE Transactions on Computers. 39, 7, p. 889-905 17 p.

研究成果: Article

2 引用 (Scopus)

3D NoC with inductive-coupling links for building-block SiPs

Take, Y., Matsutani, H., Sasaki, D., Koibuchi, M., Kuroda, T. & Amano, H., 2014 3, : : IEEE Transactions on Computers. 63, 3, p. 748-763 16 p., 6331480.

研究成果: Article

34 引用 (Scopus)

64-Gb/s highly reliable network switch (RHiNET-2/SW) using parallel optical interconnection

Nishimura, S., Kudoh, T., Nishi, H., Yamamoto, J., Harasawa, K., Matsudaira, N., Akutsu, S. & Amano, H., 2000 12 1, : : Journal of Lightwave Technology. 18, 12, p. 1620-1627 8 p.

研究成果: Article

6 引用 (Scopus)

A Dynamically Adaptive Hardware on Dynamically Reconfigurable Processor

Amano, H., Jouraku, A. & Anjo, K., 2003 12, : : IEICE Transactions on Communications. E86-B, 12, p. 3385-3391 7 p.

研究成果: Article

10 引用 (Scopus)
公開

A fine-grained power gating control on linux monitoring power consumption of processor functional units

Koshiba, A., Wada, M., Sakamoto, R., Sato, M., Kosaka, T., Usami, K., Amano, H., Kondo, M., Nakamura, H. & Namiki, M., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 559-568 10 p.

研究成果: Article

2 引用 (Scopus)

A generalized theory based on the turn model for deadlock-free irregular networks

Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2020, : : IEICE Transactions on Information and Systems. E103D, 1, p. 101-110 10 p.

研究成果: Article

公開

A layout-oriented routing method for low-latency HPC networks

Kawano, R., Nakahara, H., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 12, : : IEICE Transactions on Information and Systems. E100D, 12, p. 2796-2807 12 p.

研究成果: Article

1 引用 (Scopus)

A leakage efficient data TLB design for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Sunata, T., Namiki, M. & Amano, H., 2011 1, : : IEICE Transactions on Information and Systems. E94-D, 1, p. 51-59 9 p.

研究成果: Article

公開

A leakage efficient instruction TLB design for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Sunata, T., Namiki, M. & Amano, H., 2011 8, : : IEICE Transactions on Information and Systems. E94-D, 8, p. 1565-1574 10 p.

研究成果: Article

4 引用 (Scopus)
1 引用 (Scopus)

An analysis of fairness and overhead in the arbitration protocol of the IEEE futurebus standard

Yamamoto, O., Terasawa, T. & Amano, H., 1998 11 30, : : Systems and Computers in Japan. 29, 13, p. 66-77 12 p.

研究成果: Article

An analytical network performance model for SIMD processor CSX600 interconnects

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2011 1 1, : : Journal of Systems Architecture. 57, 1, p. 146-159 14 p.

研究成果: Article

26 引用 (Scopus)

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 8 1, : : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

研究成果: Article

A novel channel assignment method to ensure deadlock-freedom for deterministic routing

Kawano, R., Nakahara, H., Tade, S., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 8, : : IEICE Transactions on Information and Systems. E100D, 8, p. 1798-1806 9 p.

研究成果: Article

2 引用 (Scopus)

A performance evaluation of the multiprocessor testbed ATTEMPT-0

Terasawa, T., Yamamoto, O., Kudoh, T. & Amano, H., 1995 5, : : Parallel Computing. 21, 5, p. 701-730 30 p.

研究成果: Article

2 引用 (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

研究成果: Article

17 引用 (Scopus)

A query‐based parallel logic simulation algorithm

Kudoh, T., Kimura, T., Amano, H. & Terasawa, T., 1993, : : Systems and Computers in Japan. 24, 2, p. 11-21 11 p.

研究成果: Article

3 引用 (Scopus)

A routing algorithm for multihop WDM ring

Bong, X., Kudoh, T. & Amano, H., 1999 1 1, : : IEICE Transactions on Information and Systems. E82-D, 2, p. 422-430 9 p.

研究成果: Article

A scalable 3D heterogeneous multicore with an inductive ThruChip interface

Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 11 1, : : IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

研究成果: Article

21 引用 (Scopus)

A simple data transfer technique using local address for networks-on-chips

Koibuchi, M., Anjo, K., Yamada, Y., Jouraku, A. & Amano, H., 2006 12 1, : : IEEE Transactions on Parallel and Distributed Systems. 17, 12, p. 1425-1437 13 p.

研究成果: Article

16 引用 (Scopus)

A study on snoop cache systems for single-chip multiprocessors

Terasawa, T., Inoue, K., Kurosawa, H. & Amano, H., 1998 2, : : Systems and Computers in Japan. 28, 2, p. 62-72 11 p.

研究成果: Article

A switch-tagged routing methodology for PC clusters with VLAN Ethernet

Koibuchi, M., Otsuka, T., Kudoh, T. & Amano, H., 2011 1 1, : : IEEE Transactions on Parallel and Distributed Systems. 22, 2, p. 217-230 14 p., 5445093.

研究成果: Article

4 引用 (Scopus)
8 引用 (Scopus)

A toolchain for dynamic function off-load on CPU-FPGA platforms

Miyajima, T., Thomas, D. & Amano, H., 2015 1 1, : : Journal of information processing. 23, 2, p. 153-162 10 p.

研究成果: Article

1 引用 (Scopus)

Automatic pipeline construction focused on similarity of rate law functions for an FPGA-based biochemical simulator

Yamada, H., Ogawa, Y., Ooya, T., Ishimori, T., Osana, Y., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2010 12 1, : : IPSJ Transactions on System LSI Design Methodology. 3, p. 244-256 13 p.

研究成果: Article

2 引用 (Scopus)

Body bias domain partitioning size exploration for a coarse grained reconfigurable accelerator

Matsushita, Y., Okuhara, H., Masuyama, K., Fujita, Y., Kawano, R. & Amano, H., 2017 12 1, : : IEICE Transactions on Information and Systems. E100D, 12, p. 2828-2836 9 p.

研究成果: Article

Body bias optimization for real-time systems

Torres, C. C. C., Yasudo, R. & Amano, H., 2020 3, : : Journal of Low Power Electronics and Applications. 10, 1, 8.

研究成果: Article

公開

Code compression with split echo instructions

Stubdal, I., Karaduman, A. & Amano, H., 2009 1 1, : : IEICE Transactions on Information and Systems. E92-D, 9, p. 1650-1656 7 p.

研究成果: Article

1 引用 (Scopus)

Cool mega-arrays: Ultralow-power reconfigurable accelerator chips

Ozaki, N., Yasuda, Y., Izawa, M., Saito, Y., Ikebuchi, D., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 11 1, : : IEEE Micro. 31, 6, p. 6-18 13 p., 6060791.

研究成果: Article

39 引用 (Scopus)
1 引用 (Scopus)

Design and implementation fine-grained power gating on microprocessor functional units

Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011 12 5, : : IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

研究成果: Article

3 引用 (Scopus)

Design and implementation of reconfigurable sensing system for networked robots

Miyajima, A., Nukata, K., Amano, H. & Anzai, Y., 1998 1 1, : : Advanced Robotics. 13, 3, p. 253-254 2 p.

研究成果: Article

Design and Implementation of RHiNET-2/NI0: A Reconfigurable Network Interface for Cluster Computing

Yokoyama, T., Izu, N., Tsuchiya, J. I., Watanabe, K., Amano, H. & Kudoh, T., 2003 5, : : IEICE Transactions on Information and Systems. E86-D, 5, p. 789-795 7 p.

研究成果: Article

1 引用 (Scopus)
1 引用 (Scopus)
3 引用 (Scopus)