• 2575 引用
  • 23 h指数
1983 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

フィルター
Article
2020

A generalized theory based on the turn model for deadlock-free irregular networks

Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2020 1 1, : : IEICE Transactions on Information and Systems. E103D, 1, p. 101-110 10 p.

研究成果: Article

公開

Body bias optimization for real-time systems

Torres, C. C. C., Yasudo, R. & Amano, H., 2020 3, : : Journal of Low Power Electronics and Applications. 10, 1, 8.

研究成果: Article

公開
2019
公開
2018
1 引用 (Scopus)
8 引用 (Scopus)
1 引用 (Scopus)
3 引用 (Scopus)

Optimization of body biasing for variable pipelined coarse-grained reconfigurable architectures

Kojima, T., Ando, N., Okuhara, H., Doan, N. A. V. & Amano, H., 2018 6 1, : : IEICE Transactions on Information and Systems. E101D, 6, p. 1532-1540 9 p.

研究成果: Article

1 引用 (Scopus)

Proxy responses by FPGA-based switch for MapReduce stragglers

Mitsuzuka, K., Koibuchi, M., Amano, H. & Matsutani, H., 2018 9 1, : : IEICE Transactions on Information and Systems. E101D, 9, p. 2258-2268 11 p.

研究成果: Article

2 引用 (Scopus)
2017

A layout-oriented routing method for low-latency HPC networks

Kawano, R., Nakahara, H., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 12 1, : : IEICE Transactions on Information and Systems. E100D, 12, p. 2796-2807 12 p.

研究成果: Article

1 引用 (Scopus)

A novel channel assignment method to ensure deadlock-freedom for deterministic routing

Kawano, R., Nakahara, H., Tade, S., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 8 1, : : IEICE Transactions on Information and Systems. E100D, 8, p. 1798-1806 9 p.

研究成果: Article

2 引用 (Scopus)

Body bias domain partitioning size exploration for a coarse grained reconfigurable accelerator

Matsushita, Y., Okuhara, H., Masuyama, K., Fujita, Y., Kawano, R. & Amano, H., 2017 12 1, : : IEICE Transactions on Information and Systems. E100D, 12, p. 2828-2836 9 p.

研究成果: Article

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Yasudo, R., Matsutani, H., Koibuchi, M., Amano, H. & Nakamura, T., 2017 4 1, : : IEEE Transactions on Computers. 66, 4, p. 702-716 15 p., 7562562.

研究成果: Article

2 引用 (Scopus)

The first 25 years of the FPL conference: Significant papers

Leong, P. H. W., Amano, H., Anderson, J., Bertels, K., Cardoso, J. M. P., Diessel, O., Gogniat, G., Hutton, M., Lee, J., Luk, W., Lysaght, P., Platzner, M., Prasanna, V. K., Rissa, T., Silvano, C., So, H. K. H. & Wang, Y., 2017 3, : : ACM Transactions on Reconfigurable Technology and Systems. 10, 2, 15.

研究成果: Article

1 引用 (Scopus)
2016

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 8 1, : : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

研究成果: Article

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

Kagami, T., Matsutani, H., Koibuchi, M., Take, Y., Kuroda, T. & Amano, H., 2016 2, : : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 2, p. 493-506 14 p., 7086053.

研究成果: Article

15 引用 (Scopus)
2 引用 (Scopus)
2 引用 (Scopus)

Optical network technologies for HPC: Computer-architects point of view

Koibuchi, M., Fujiwara, I., Ishii, K., Namiki, S., Chaix, F., Matsutani, H., Amano, H. & Kudoh, T., 2016 3 25, : : IEICE Electronics Express. 13, 6

研究成果: Article

13 引用 (Scopus)
10 引用 (Scopus)
2015

A fine-grained power gating control on linux monitoring power consumption of processor functional units

Koshiba, A., Wada, M., Sakamoto, R., Sato, M., Kosaka, T., Usami, K., Amano, H., Kondo, M., Nakamura, H. & Namiki, M., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 559-568 10 p.

研究成果: Article

2 引用 (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 7 1, : : IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

研究成果: Article

17 引用 (Scopus)

A toolchain for dynamic function off-load on CPU-FPGA platforms

Miyajima, T., Thomas, D. & Amano, H., 2015 1 1, : : Journal of information processing. 23, 2, p. 153-162 10 p.

研究成果: Article

1 引用 (Scopus)
2014

3D NoC with inductive-coupling links for building-block SiPs

Take, Y., Matsutani, H., Sasaki, D., Koibuchi, M., Kuroda, T. & Amano, H., 2014 3, : : IEEE Transactions on Computers. 63, 3, p. 748-763 16 p., 6331480.

研究成果: Article

34 引用 (Scopus)
2 引用 (Scopus)

Reconfigurable out-of-order system for fluid dynamics computation using unstructured mesh

Akamine, T., Abu Talip, M. S., Osana, Y., Fujita, N. & Amano, H., 2014 5, : : IEICE Transactions on Information and Systems. E96-D, 5, p. 1225-1234 10 p.

研究成果: Article

1 引用 (Scopus)
2013

A scalable 3D heterogeneous multicore with an inductive ThruChip interface

Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 11 1, : : IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

研究成果: Article

21 引用 (Scopus)

Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

Nakamura, H., Wang, W., Ohta, Y., Usami, K., Amano, H., Kondo, M. & Namiki, M., 2013 4, : : IEICE Transactions on Electronics. E96-C, 4, p. 404-412 9 p.

研究成果: Article

High-speed fully-adaptable CRC accelerators

Akagic, A. & Amano, H., 2013 6, : : IEICE Transactions on Information and Systems. E96-D, 6, p. 1299-1308 10 p.

研究成果: Article

Vertical link on/off regulations for inductive-coupling based wireless 3-D NoCs

Zhang, H., Matsutani, H., Take, Y., Kuroda, T. & Amano, H., 2013 12, : : IEICE Transactions on Information and Systems. E96-D, 12, p. 2753-2764 12 p.

研究成果: Article

2012

Partial reconfiguration of flux limiter functions in MUSCL scheme using FPGA

Abu Talip, M. S., Akamine, T., Osana, Y., Fujita, N. & Amano, H., 2012 10, : : IEICE Transactions on Information and Systems. E95-D, 10, p. 2369-2376 8 p.

研究成果: Article

2011

A leakage efficient data TLB design for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Sunata, T., Namiki, M. & Amano, H., 2011 1, : : IEICE Transactions on Information and Systems. E94-D, 1, p. 51-59 9 p.

研究成果: Article

公開

A leakage efficient instruction TLB design for embedded processors

Lei, Z., Xu, H., Ikebuchi, D., Sunata, T., Namiki, M. & Amano, H., 2011 8, : : IEICE Transactions on Information and Systems. E94-D, 8, p. 1565-1574 10 p.

研究成果: Article

An analytical network performance model for SIMD processor CSX600 interconnects

Nishikawa, Y., Koibuchi, M., Yoshimi, M., Miura, K. & Amano, H., 2011 1 1, : : Journal of Systems Architecture. 57, 1, p. 146-159 14 p.

研究成果: Article

A switch-tagged routing methodology for PC clusters with VLAN Ethernet

Koibuchi, M., Otsuka, T., Kudoh, T. & Amano, H., 2011 1 1, : : IEEE Transactions on Parallel and Distributed Systems. 22, 2, p. 217-230 14 p., 5445093.

研究成果: Article

4 引用 (Scopus)

Cool mega-arrays: Ultralow-power reconfigurable accelerator chips

Ozaki, N., Yasuda, Y., Izawa, M., Saito, Y., Ikebuchi, D., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 11 1, : : IEEE Micro. 31, 6, p. 6-18 13 p., 6060791.

研究成果: Article

39 引用 (Scopus)

Design and implementation fine-grained power gating on microprocessor functional units

Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011 12 5, : : IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

研究成果: Article

3 引用 (Scopus)
29 引用 (Scopus)

Prediction router: A low-latency on-chip router architecture with multiple predictors

Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2011 5 5, : : IEEE Transactions on Computers. 60, 6, p. 783-799 17 p., 5703069.

研究成果: Article

17 引用 (Scopus)
2010

Automatic pipeline construction focused on similarity of rate law functions for an FPGA-based biochemical simulator

Yamada, H., Ogawa, Y., Ooya, T., Ishimori, T., Osana, Y., Yoshimi, M., Nishikawa, Y., Funahashi, A., Hiroi, N., Amano, H., Shibata, Y. & Oguri, K., 2010 12 1, : : IPSJ Transactions on System LSI Design Methodology. 3, p. 244-256 13 p.

研究成果: Article

2 引用 (Scopus)
2009

Code compression with split echo instructions

Stubdal, I., Karaduman, A. & Amano, H., 2009 1 1, : : IEICE Transactions on Information and Systems. E92-D, 9, p. 1650-1656 7 p.

研究成果: Article

1 引用 (Scopus)

Fat H-Tree: A cost-efficient tree-based on-chip network

Matsutani, H., Koibuchi, M., Yamada, Y., Hsu, D. F. & Amano, H., 2009 6 4, : : IEEE Transactions on Parallel and Distributed Systems. 20, 8, p. 1126-1141 16 p.

研究成果: Article

18 引用 (Scopus)
2008
4 引用 (Scopus)