• 2609 引用
  • 26 h指数
19962019

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

フィルター
Paper
2012

A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Hiraku, Y., Hayashi, I., Chung, H., Kuroda, T. & Ishikuro, H., 2012 12 1, p. 33-36. 4 p.

研究成果: Paper

9 引用 (Scopus)

A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating

Sekimoto, R., Shikata, A., Yoshioka, K., Kuroda, T. & Ishikuro, H., 2012 12 1, p. 161-164. 4 p.

研究成果: Paper

4 引用 (Scopus)
2005

A low-IF CMOS single-chip bluetooth EDR transmitter with digital I/Q mismatch trimming circuit

Miyashita, D., Ishikuro, H., Shimada, T., Tanzawa, T., Kousai, S., Kobayashi, H., Majima, H., Agawa, K., Hamada, M. & Hatori, F., 2005 12 1, p. 298-301. 4 p.

研究成果: Paper

7 引用 (Scopus)
1999

Narrow channel MOSFET memory based on silicon nanocrystals and charge storage characteristics

Shi, Y., Yuan, X. L., Gu, S. L., Zhang, R., Zheng, Y. D., Saito, K., Ishikuro, H. & Hiramoto, T., 1999, p. 136-137. 2 p.

研究成果: Paper

1998

Effects of body reverse pulse bias on geometric component of charge pumping current in FD SOI MOSFETs

Duyet, T. N., Ishikuro, H., Takamiya, M., Saraya, T. & Hiramoto, T., 1998 12 1, p. 79-80. 2 p.

研究成果: Paper

2 引用 (Scopus)

Silicon nano-crystals based MOS memory and effects of traps on charge storage characteristics

Shi, Y., Gu, S. L., Yuan, X. L., Zheng, Y. D., Saito, K., Ishikuro, H. & Hiramoto, T., 1998, p. 838-841. 4 p.

研究成果: Paper

8 引用 (Scopus)
1997

Energy spectrum of the quantum-dot in a Si single-electron device

Ishikuro, H. & Hiramoto, T., 1997 1 1, p. 84-85. 2 p.

研究成果: Paper

3 引用 (Scopus)
1996

Floating body effects in 0.15 μm partially depleted SOI MOSFETs below 1 V

Saraya, T., Takamiya, M., Duyet, T. N., Tanaka, T., Ishikuro, H., Hiramoto, T. & Ikoma, T., 1996 12 1, p. 70-71. 2 p.

研究成果: Paper

11 引用 (Scopus)