松谷 宏紀

研究成果

年別の研究成果 2005 2012 2013 2015 2016 2017 2018 2019 2020 2021 2022

• 114 Conference contribution
• 36 Article
• 2 Paper
• 2 Conference article
• 4 その他
  • 2 Editorial
  • 1 Chapter
  • 1 Review article

年別の研究成果

年別の研究成果

検索結果

• Article

  3D NoC with inductive-coupling links for building-block SiPs

  Take, Y., Matsutani, H., Sasaki, D., Koibuchi, M., Kuroda, T. & Amano, H., 2014 3月, In: IEEE Transactions on Computers. 63, 3, p. 748-763 16 p., 6331480.

  研究成果: Article › 査読

  • Network on chip 100%
  • Chip 63%
  • Building Blocks 56%
  • Network-on-chip 56%
  • Transceivers 47%
  46 被引用数 (Scopus)

• Adaptive data compression on 3D network-on-chips

  He, Y., Matsutani, H., Sasaki, H. & Nakamura, H., 2012, In: IPSJ Online Transactions. 5, 1, p. 13-20 8 p.

  研究成果: Article › 査読

  • Network-on-chip 100%
  • Data compression 96%
  • Compressibility 49%
  • Bandwidth 27%
  • Degradation 20%
  3 被引用数 (Scopus)

• A generalized theory based on the turn model for deadlock-free irregular networks

  Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2020, In: IEICE Transactions on Information and Systems. E103D, 1, p. 101-110 10 p.

  研究成果: Article › 査読

  Open Access

  • Throughput 100%
  • Routing algorithms 73%
  • Network performance 69%
  • Topology 48%

• A hardware-based caching system on FPGA NIC for Blockchain

  Sakakibara, Y., Morishima, S., Nakamura, K. & Matsutani, H., 2018 5月, In: IEICE Transactions on Information and Systems. E101D, 5, p. 1350-1360 11 p.

  研究成果: Article › 査読

  • Blockchain 100%
  • Interfaces (computer) 80%
  • Field programmable gate arrays (FPGA) 69%
  • Computer hardware 50%
  • Servers 41%
  15 被引用数 (Scopus)

• A layout-oriented routing method for low-latency HPC networks

  Kawano, R., Nakahara, H., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 12月, In: IEICE Transactions on Information and Systems. E100D, 12, p. 2796-2807 12 p.

  研究成果: Article › 査読

  • Scalability 100%
  • Switches 89%
  • Throughput 86%
  2 被引用数 (Scopus)

• A link removal methodology for application-specific networks-on-chip on FPGAs

  Wang, D., Matsutani, H., Koibuchi, M. & Amano, H., 2009, In: IEICE Transactions on Information and Systems. E92-D, 4, p. 575-583 9 p.

  研究成果: Article › 査読

  • Network-on-chip 100%
  • Field programmable gate arrays (FPGA) 72%
  • Computer hardware 51%
  • Topology 40%
  • Image recognition 33%

• An area-efficient recurrent neural network core for unsupervised time-series anomaly detection

  SAKUMA, T. & MATSUTANI, H., 2021 6月 1, In: IEICE Transactions on Electronics. 1, 6, p. 247-256 10 p.

  研究成果: Article › 査読

  Open Access

  • Anomaly detection 100%
  • Recurrent neural networks 99%
  • Time series 83%
  • Computer hardware 56%
  • Machine learning 46%

• A neural network-based on-device learning anomaly detector for edge devices

  Tsukada, M., Kondo, M. & Matsutani, H., 2020 7月 1, In: IEEE Transactions on Computers. 69, 7, p. 1027-1044 18 p., 9000710.

  研究成果: Article › 査読

  Open Access

  • Concept Drift 100%
  • Detector 61%
  • Anomaly 59%
  • Power Consumption 55%
  • Server 55%
  30 被引用数 (Scopus)

• An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm^∗

  Sugiura, K. & Matsutani, H., 2021, In: IEICE Transactions on Information and Systems. E104D, 6, p. 789-800 12 p.

  研究成果: Article › 査読

  Open Access

  • Field programmable gate arrays (FPGA) 100%
  • Throughput 56%
  • Robots 52%
  • Intellectual property core 51%
  • Mobile robots 36%
  4 被引用数 (Scopus)

• An FPGA-based change-point detection for 10Gbps packet stream

  Iwata, T., Nakamura, K., Tokusashi, Y. & Matsutani, H., 2019, In: IEICE Transactions on Information and Systems. E102D, 12, p. 2366-2376 11 p.

  研究成果: Article › 査読

  Open Access

  • Interfaces (computer) 100%
  • Field programmable gate arrays (FPGA) 86%
  • Ethernet 81%
  • Time series 45%
  • Throughput 36%

• An FPGA-based optimizer design for distributed deep learning with multiple GPUs

  Itsubo, T., Koibuchi, M., Amano, H. & Matsutani, H., 2021, In: IEICE Transactions on Information and Systems. E104D, 12, p. 2057-2067 11 p.

  研究成果: Article › 査読

  Open Access

  • Graphics processing unit 100%
  • Deep learning 95%
  • Field programmable gate arrays (FPGA) 87%
  • Ethernet 62%
  • Switches 55%

• An On-Device Federated Learning Approach for Cooperative Model Update between Edge Devices

  Ito, R., Tsukada, M. & Matsutani, H., 2021, In: IEEE Access. 9, p. 92986-92998 13 p., 9467340.

  研究成果: Article › 査読

  Open Access

  • Communication 100%
  • Amount 46%
  • Time 39%
  • Anomaly detection 16%
  • Neural networks 9%

• A novel channel assignment method to ensure deadlock-freedom for deterministic routing

  Kawano, R., Nakahara, H., Tade, S., Fujiwara, I., Matsutani, H., Koibuchi, M. & Amano, H., 2017 8月, In: IEICE Transactions on Information and Systems. E100D, 8, p. 1798-1806 9 p.

  研究成果: Article › 査読

  • Scalability 100%
  • Switches 89%
  • Topology 84%
  • Data storage equipment 75%
  2 被引用数 (Scopus)

• An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit

  Tsukada, M. & Matsutani, H., 2022, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 105, 3, p. 437-447 11 p.

  研究成果: Article › 査読

  Open Access

  • Extreme Learning Machine 100%
  • Digital Circuits 85%
  • Overflow 69%
  • Digital circuits 58%
  • Optimization Methods 57%

• A port combination methodology for application-specific networks-on-chip on FPGAS

  Wang, D., Matsutani, H., Koibuchi, M. & Amano, H., 2007 12月, In: IEICE Transactions on Information and Systems. E90-D, 12, p. 1914-1922 9 p.

  研究成果: Article › 査読

  • Network-on-chip 100%
  • Computer hardware 25%
  • Routers 14%
  • Degradation 10%
  • Scheduling 10%

• A scalable 3D heterogeneous multicore with an inductive ThruChip interface

  Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 11月, In: IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

  研究成果: Article › 査読

  • Particle accelerators 100%
  • Linux 51%
  • Program processors 41%
  • Costs 37%
  • Energy utilization 34%
  26 被引用数 (Scopus)

• A traffic-aware memory-cube network using bypassing

  Shikama, Y., Kawano, R., Matsutani, H., Amano, H., Nagasaka, Y., Fukumoto, N. & Koibuchi, M., 2022 4月, In: Microprocessors and Microsystems. 90, 104471.

  研究成果: Article › 査読

  • Routers 100%
  • Data storage equipment 88%
  • Topology 42%
  • Network routing 25%
  • Packet networks 24%
  1 被引用数 (Scopus)

• A Universal LiDAR SLAM Accelerator System on Low-Cost FPGA

  Sugiura, K. & Matsutani, H., 2022, In: IEEE Access. 10, p. 26931-26947 17 p.

  研究成果: Article › 査読

  Open Access

  • Particle accelerators 100%
  • Field programmable gate arrays (FPGA) 80%
  • Costs 37%
  • Time 35%
  • Robots 18%
  3 被引用数 (Scopus)

• Designing High-Performance Interconnection Networks with Host-Switch Graphs

  Yasudo, R., Koibuchi, M., Nakano, K., Matsutani, H. & Amano, H., 2019 2月 1, In: IEEE Transactions on Parallel and Distributed Systems. 30, 2, p. 315-330 16 p., 8428449.

  研究成果: Article › 査読

  • High Performance 100%
  • Interconnection Networks 93%
  • Switch 83%
  • Switches 55%
  • Network Topology 38%
  5 被引用数 (Scopus)

• Designing low-diameter interconnection networks with multi-ported host-switch graphs

  Yasudo, R., Nakano, K., Koibuchi, M., Matsutani, H. & Amano, H., 2020, (Accepted/In press) In: Concurrency Computation Practice and Experience.

  研究成果: Article › 査読

  • Interconnection Networks 100%
  • Switch 88%
  • Switches 58%
  • Graph in graph theory 37%
  • InfiniBand 30%
  3 被引用数 (Scopus)

• Dynamic power consumption optimization for inductive-coupling based wireless 3D NoCs

  Zhang, H., Matsutani, H., Koibuchi, M. & Amano, H., 2014 2月, In: IPSJ Transactions on System LSI Design Methodology. 7, p. 27-36 10 p.

  研究成果: Article › 査読

  • Electric power utilization 100%
  • Network-on-chip 76%
  • Telecommunication links 62%
  • System-in-package 46%
  • Topology 45%
  2 被引用数 (Scopus)

• Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces

  Kagami, T., Matsutani, H., Koibuchi, M., Take, Y., Kuroda, T. & Amano, H., 2016 2月, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 2, p. 493-506 14 p., 7086053.

  研究成果: Article › 査読

  • Time division multiple access 100%
  • Carrier sense multiple access 81%
  • Network-on-chip 49%
  • Communication 44%
  • Energy transfer 25%
  17 被引用数 (Scopus)

• Fat H-Tree: A cost-efficient tree-based on-chip network

  Matsutani, H., Koibuchi, M., Yamada, Y., Hsu, D. F. & Amano, H., 2009, In: IEEE Transactions on Parallel and Distributed Systems. 20, 8, p. 1126-1141 16 p.

  研究成果: Article › 査読

  • Network on chip 100%
  • Oils and fats 58%
  • Network-on-chip 56%
  • Costs 36%
  • Resources 10%
  21 被引用数 (Scopus)

• High-Performance with an In-GPU Graph Database Cache

  Morishima, S. & Matsutani, H., 2017 11月 1, In: IT Professional. 19, 6, p. 58-64 7 p., 8123479.

  研究成果: Article › 査読

  • Graph Databases 100%
  • Graphics processing unit 66%
  • Complex networks 24%
  • Ethernet 24%
  • Logistics 21%
  3 被引用数 (Scopus)

• In-GPU cache for acceleration of anomaly detection in blockchain

  Morishima, S. & Matsutani, H., 2020 8月 1, In: IEICE Transactions on Information and Systems. E103D, 8, p. 1814-1824 11 p.

  研究成果: Article › 査読

  Open Access

  • Blockchain 100%
  • Anomaly detection 89%
  • Graphics processing unit 79%
  • Feature extraction 65%
  • K-means clustering 19%

• Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches

  Tokusashi, Y. & Matsutani, H., 2017 9月 1, In: IEEE Micro. 37, 5, p. 44-51 8 p., 8065000.

  研究成果: Article › 査読

  • Field programmable gate arrays (FPGA) 100%
  • Dynamic random access storage 47%
  • Particle accelerators 41%
  • Throughput 28%
  • Computer hardware 23%
  7 被引用数 (Scopus)

• Multi-voltage variable pipeline routers with the same clock frequency for low-power network-on-chips systems

  Ahmed, A. B., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2016 8月 1, In: IEICE Transactions on Electronics. E99C, 8, p. 909-917 9 p.

  研究成果: Article › 査読

  • Pipeline 100%
  • Network-on-chip 96%
  • Routers 82%
  • Clocks 73%
  • Pipelines 65%
  2 被引用数 (Scopus)

• Novel chip stacking methods to extend both horizontally and vertically for many-core architectures with ThrouChip interface

  Nakahara, H., Ozaki, T., Matsutani, H., Koibuchi, M. & Amano, H., 2016 12月, In: IEICE Transactions on Information and Systems. E99D, 12, p. 2871-2880 10 p.

  研究成果: Article › 査読

  • System-on-chip 100%
  • Masks 92%
  • Large scale systems 83%
  • Costs 74%
  2 被引用数 (Scopus)

• Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

  Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 4月, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

  研究成果: Article › 査読

  • Routers 100%
  • Network-on-chip 19%
  • Application programs 15%
  • Communication 8%
  34 被引用数 (Scopus)

• Prediction router: A low-latency on-chip router architecture with multiple predictors

  Matsutani, H., Koibuchi, M., Amano, H. & Yoshinaga, T., 2011, In: IEEE Transactions on Computers. 60, 6, p. 783-799 17 p., 5703069.

  研究成果: Article › 査読

  • Router 100%
  • Latency 87%
  • Chip 85%
  • Architecture 74%
  • Routers 64%
  23 被引用数 (Scopus)

• Proxy responses by FPGA-based switch for MapReduce stragglers

  Mitsuzuka, K., Koibuchi, M., Amano, H. & Matsutani, H., 2018 9月, In: IEICE Transactions on Information and Systems. E101D, 9, p. 2258-2268 11 p.

  研究成果: Article › 査読

  • Field programmable gate arrays (FPGA) 100%
  • Switches 87%
  • Ethernet 50%
  • Communication 12%
  • Experiments 8%
  2 被引用数 (Scopus)

• Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

  Yasudo, R., Matsutani, H., Koibuchi, M., Amano, H. & Nakamura, T., 2017 4月 1, In: IEEE Transactions on Computers. 66, 4, p. 702-716 15 p., 7562562.

  研究成果: Article › 査読

  • Network on chip 100%
  • Router 74%
  • Decentralized 64%
  • Network-on-chip 56%
  • Routers 47%
  2 被引用数 (Scopus)

• Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects

  Fujiwara, I., Koibuchi, M., Matsutani, H. & Casanova, H., 2015 7月 1, In: IEEE Transactions on Parallel and Distributed Systems. 26, 7, p. 2051-2060 10 p., 6860278.

  研究成果: Article › 査読

  • Interconnect 100%
  • Latency 88%
  • Swap 88%
  • Topology 47%
  • Cable 42%
  17 被引用数 (Scopus)

• The dependable responsive multithreaded processor for distributed real-time systems

  Suito, K., Ueda, R., Fujii, K., Kogo, T., Matsutani, H. & Yamasaki, N., 2012, In: IEEE Micro. 32, 6, p. 52-61 10 p., 6353408.

  研究成果: Article › 査読

  • Real time systems 100%
  • Data storage equipment 61%
  • Computer hardware 58%
  • Electric potential 51%
  • Sensors 51%
  17 被引用数 (Scopus)

• Traffic-independent multi-path routing for high-throughput data center networks

  Kawano, R., Yasudo, R., Matsutani, H., Koibuchi, M. & Amano, H., 2020 12月 1, In: IEICE Transactions on Information and Systems. E103D, 12, p. 2471-2479 9 p.

  研究成果: Article › 査読

  Open Access

  • Throughput 100%
  • Warehouses 32%
  • Big data 25%
  • Switches 20%
  1 被引用数 (Scopus)

• Vertical link on/off regulations for inductive-coupling based wireless 3-D NoCs

  Zhang, H., Matsutani, H., Take, Y., Kuroda, T. & Amano, H., 2013 12月, In: IEICE Transactions on Information and Systems. E96-D, 12, p. 2753-2764 12 p.

  研究成果: Article › 査読

  • Telecommunication links 100%
  • Routers 41%
  • Transmitters 36%
  • Electric power utilization 32%
  • Network-on-chip 24%