Naoaki Yamanaka

1997

Extended multicasting technique to allow multiple destinations per output port in ATM switches

Agrawal, J. P. & Yamanaka, N., 1997, In: IEEE Communications Letters. 1, 4, p. 117-118 2 p.

研究成果: Article › 査読

Flexible multi-QoS logical ATM network (full-net)

Yamanaka, N. & Oki, E., 1997 6月, In: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi). 80, 6, p. 47-58 12 p.

研究成果: Article › 査読

High-performance packaging technology for very-high-speed ATM switching systems

Kaizu, K., Kishimoto, T., Sasaki, S. I., Yamanaka, N. & Genda, K., 1997 3月 1, In: NTT Review. 9, 2, p. 36-45 10 p.

研究成果: Article › 査読

Some new suvivability measures for network analysis and design

Moitra, S. D., Oki, E. & Yamanaka, N., 1997, In: IEICE Transactions on Communications. E80-B, 4, p. 625-631 7 p.

研究成果: Article › 査読

10 被引用数 (Scopus)

TORUS: Terabit-per-second ATM switching system architecture based on distributed internal speed-up ATM switch

Genda, K. & Yamanaka, N., 1997 6月, In: IEEE Journal on Selected Areas in Communications. 15, 5, p. 817-828 12 p.

研究成果: Article › 査読

12 被引用数 (Scopus)

Very-high-speed ATM switching system technologies

Yamanaka, N., Doi, Y., Fukuda, H., Takenaka, T. & Yashiro, Z. I., 1997 3月 1, In: NTT Review. 9, 2, p. 12-19 8 p.

研究成果: Article › 査読

1998

Advanced atm switching system hardware technologies based on mcm-d for atm line interface circuits

Kawamura, T., Yamanaka, N. & Kaizu, K., 1998 1月 1, In: IEICE Transactions on Communications. E81-B, 2, p. 482-487 6 p.

研究成果: Article › 査読

A high-speed CAC scheme in ATM networks by using virtual requests for connection

Oki, E. & Yamanaka, N., 1998 1月 1, In: IEICE Transactions on Communications. E81-B, 10, p. 1927-1930 4 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

A high-speed tandem-crosspoint ATM switch architecture with input and output buffers

Oki, E. & Yamanaka, N., 1998 1月 1, In: IEICE Transactions on Communications. E81-B, 2, p. 215-222 8 p.

研究成果: Article › 査読

15 被引用数 (Scopus)

ALPEN: An ATM multi-protocol emulation network based on periodical performance checks between edge nodes

Yamanaka, N., Shiomoto, K. & Hasegawa, H., 1998 8月, In: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi). 81, 8, p. 19-31 13 p.

研究成果: Article › 査読

An admission control scheme based on measurements of instantaneous utilization

Shiomoto, K. & Yamanaka, N., 1998 11月, In: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi). 81, 11, p. 1-13 13 p.

研究成果: Article › 査読

A new multiple QoS control scheme with equivalent-window CAC in ATM networks

Oki, E., Yamanaka, N., Shiomoto, K. & Moitra, S. D., 1998 1月 1, In: IEICE Transactions on Communications. E81-B, 7, p. 1462-1473 12 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

Architectural choices in large scale ATM switches

Turner, J. & Yamanaka, N., 1998, In: IEICE Transactions on Communications. E81-B, 2, p. 120-136 17 p.

研究成果: Article › 査読

73 被引用数 (Scopus)

A simple bandwidth management strategy based on measurements of instantaneous virtual path utilization in ATM networks

Shiomoto, K., Chaki, S. & Yamanaka, N., 1998, In: IEEE/ACM Transactions on Networking. 6, 5, p. 625-634 10 p.

研究成果: Article › 査読

27 被引用数 (Scopus)

Breakthrough technologies for the high-performance electrical ATM switching system

Yamanaka, N., 1998 12月, In: Journal of Lightwave Technology. 16, 12, p. 2181-2190 10 p.

研究成果: Article › 査読

13 被引用数 (Scopus)

Compact 10Gbit/s optical transceiver/receiver set with novel cooling structure for 640Gbit/s WDM interconnection

Kawano, R., Yamanaka, N., Yasukawa, S. & Okazaki, K., 1998 9月 17, In: Electronics Letters. 34, 19, p. 1876-1877 2 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

Dynamic reference single-ended ECL input interface circuit for 80Gbit/s MCMs

Kawano, R., Yamanaka, N., Oki, E. & Kawamura, T., 1998 8月 20, In: Electronics Letters. 34, 17, p. 1641-1643 3 p.

研究成果: Article › 査読

Flexible hardware design methodology for high-performance atm switching system using real-time emulation technique

Matsumura, T., Yamanaka, N., Yamaguchi, R. & Ishikawa, K., 1998 1月 1, In: IEICE Transactions on Communications. E81-B, 2, p. 466-471 6 p.

研究成果: Article › 査読

Impact of Multimedia Traffic Characteristics on ATM Network Configuration

Oki, E. & Yamanaka, N., 1998 1月 1, In: Journal of Network and Systems Management. 6, 4, p. 377-398 22 p.

研究成果: Article › 査読

8 被引用数 (Scopus)

Tandem-crosspoint ATM switch with input and output buffers

Oki, E. & Yamanaka, N., 1998, In: IEEE Communications Letters. 2, 7, p. 189-191 3 p.

研究成果: Article › 査読

10 被引用数 (Scopus)

User-programmable flexible ATM network architecture, active-ATM

Yamanaka, N., Oki, E., Hasegawa, H. & Chen, T. M., 1998 1月 1, In: IEICE Transactions on Communications. E81-B, 11, p. 2233-2236 4 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

1999

10-Gb/s (1.25 Gb/s×8) 4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration

Oki, E., Yamanaka, N., Ohtomo, Y., Okazaki, K. & Kawano, R., 1999 12月, In: IEEE Journal of Solid-State Circuits. 34, 12, p. 1921-1934 14 p.

研究成果: Article › 査読

21 被引用数 (Scopus)

80 Gbit/s ATM switch MCM based on multilayer ceramic technology

Okazaki, K., Sugiura, N., Harada, A., Yamanaka, N. & Oki, E., 1999 11月 25, In: Electronics Letters. 35, 24, p. 2074-2076 3 p.

研究成果: Article › 査読

80Gbit/s optical-l/O-interface ATM-switch MCM

Kawano, R., Yamanaka, N., Oki, E., Okazaki, K., Yasukawa, S., Ohki, A., Sato, N., Katsura, K. & Ando, Y., 1999, In: Electronics Letters. 35, 16, p. 1356-1358 3 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

A dynamic reference single-ended ECL input interface circuit for MCM-Based 80-Gbps ATM switch

Kawano, R., Yamanaka, N., Oki, E. & Kawamura, T., 1999 1月 1, In: IEICE Transactions on Electronics. E82-C, 3, p. 519-524 6 p.

研究成果: Article › 査読

DTM: Dynamic transfer mode based on dynamically assigned short-hold time-slot relay

Yamanaka, N. & Shiomotq, K., 1999, In: IEICE Transactions on Communications. E82-B, 2, p. 439-445 7 p.

研究成果: Article › 査読

3 被引用数 (Scopus)

Dynamic burst transfer time-slot-base network

Shiomoto, K. & Yamanaka, N., 1999 10月, In: IEEE Communications Magazine. 37, 10, p. 88-96 9 p.

研究成果: Article › 査読

High-speed multi-stage ATM switch based on hierarchical cell resequencing architecture and WDM interconnection

Yasukawa, S., Yamanaka, N., Oki, E. & Kawano, R., 1999, In: IEICE Transactions on Electronics. E82-C, 2, p. 219-227 9 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

High-speed multi-stage ATM switch based on hierarchical cell resequencing architecture and WDM interconnection

Yasukawa, S., Yamanaka, N., Okl, E. & Kawano, R., 1999, In: IEICE Transactions on Communications. E82-B, 2, p. 271-279 9 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

Integrated physical and logical layer design of multimedia ATM networks

Moitra, S. D., Oki, E. & Yamanaka, N., 1999, In: IEICE Transactions on Communications. E82-B, 9, p. 1531-1540 10 p.

研究成果: Article › 査読

New scheduling mechanisms for achieving fairness criteria (MCR plus equal share, maximum of MCR or Max-Min share)

Nabeshima, M. & Yamanaka, N., 1999 1月 1, In: IEICE Transactions on Communications. E82-B, 6, p. 962-966 5 p.

研究成果: Article › 査読

Performance evaluation of high-speed admission control in ATM networks based on virtual request generation

Oki, E. & Yamanaka, N., 1999 1月 1, In: IEICE Transactions on Communications. E82-B, 3, p. 473-480 8 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

Oki, E., Yamanaka, N., Okazaki, K. & Ohtomo, Y., 1999 4月 29, In: Electronics Letters. 35, 9, p. 715-716 2 p.

研究成果: Article › 査読

Scalable 3-stage ATM switch architecture using optical WDM grouped links based on dynamic bandwidth sharing

Nakai, K., Oki, E. & Yamanaka, N., 1999, In: IEICE Transactions on Electronics. E82-C, 2, p. 213-218 6 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

Scalable 3-stage ATM switch architecture using optical WDM grouped links based on dynamic bandwidth sharing

Nakal, K., Oki, E. & Yamanaka, N., 1999, In: IEICE Transactions on Communications. E82-B, 2, p. 265-270 6 p.

研究成果: Article › 査読

5 被引用数 (Scopus)

Scalable frame-synchronization circuit for highly parallel optical interconnections

Yamakoshi, K., Kawano, R. & Yamanaka, N., 1999 11月 25, In: Electronics Letters. 35, 24, p. 2117-2118 2 p.

研究成果: Article › 査読

2000

A distributed traffic control scheme for large-scale multi-stage ATM switching systems

Nakalt, K., Oku, É. & Yamanaka, N., 2000 1月 1, In: IEICE Transactions on Communications. E83-B, 2, p. 231-236 6 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

ATM flow control based on rate prediction with extrapolation under WAN environment

Hasegawa, H., Yamanaka, N. & Shiomoto, K., 2000, In: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi). 83, 7, p. 1-14 14 p.

研究成果: Article › 査読

High-speed switch system for multimedia service nodes

Yamanaka, N., Yamakoshi, K. & Kawano, R., 2000 12月 1, In: NTT R and D. 49, 12, p. 698-705 8 p.

研究成果: Article › 査読

1 被引用数 (Scopus)

OPTIMA: Scalable, multi-stage, 640-Gbit/s ATM switching system based on advanced electronic and optical WDM technologies

Yamanaka, N., Oki, E., Yasukawa, S., Kawano, R. & Okazaki, K., 2000 1月 1, In: IEICE Transactions on Communications. E83-B, 7, p. 1488-1495 8 p.

研究成果: Article › 査読

9 被引用数 (Scopus)

Performance of scalable-distributed-arbitration ATM switch supporting multiple qos classes

Okl, E., Yamanaka, N. & Nabeshima, M., 2000 1月 1, In: IEICE Transactions on Communications. E83-B, 2, p. 204-212 9 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

Scalable multi-stage cell-switching architecture: OPTIMA

Yasukawa, S., Oki, E., Nakai, K. & Yamanaka, N., 2000 12月 1, In: NTT R and D. 49, 12, p. 706-712 7 p.

研究成果: Article › 査読

2001

A 100-Gb/s throughput ATM switch MCM with a 320-channel parallel optical I/O interface

Kawano, R., Yamanaka, N., Oki, E., Yasukawa, S., Okazaki, K., Ohki, A., Usui, M., Sato, N., Katsura, K., Ando, Y., Kagawa, T. & Hikita, M., 2001 2月, In: IEEE Transactions on Advanced Packaging. 24, 1, p. 91-98 8 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

Very compact scalable 80 Gbit/s ATM switching module

Oki, E., Yamanaka, N., Okazaki, K., Kawano, R. & Ohtomo, Y., 2001 3月, In: Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi). 84, 3, p. 1-11 11 p.

研究成果: Article › 査読

2002

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS, MCM-C, and optical WDM interconnection

Yamanaka, N., Kawano, R., Oki, E., Yasukawa, S. & Okazaki, K., 2002 2月, In: IEEE Transactions on Advanced Packaging. 25, 1, p. 65-72 8 p.

研究成果: Article › 査読

3 被引用数 (Scopus)

A buffer management mechanism for achieving approximately fair bandwidth allocation in high-speed networks

Miyamura, T., Kurimoto, T., Nakagawa, K., Dhananjaya, P., Aoki, M. & Yamanaka, N., 2002 8月, In: IEICE Transactions on Communications. E85-B, 8, p. 1434-1441 8 p.

研究成果: Article › 査読

2 被引用数 (Scopus)

Active queue control scheme for achieving approximately fair bandwidth allocation

Miyamura, T., Kurimoto, T., Nakagawa, K., Dhananjaya, P., Aoki, M. & Yamanaka, N., 2002, In: IEEE International Conference on Communications. 2, p. 1269-1273 5 p.

研究成果: Article › 査読

7 被引用数 (Scopus)

A disjoint path selection scheme with shared risk link groups in GMPLS networks

Oki, E., Matsuura, N., Shiomoto, K. & Yamanaka, N., 2002 9月, In: IEEE Communications Letters. 6, 9, p. 406-408 3 p.

研究成果: Article › 査読

102 被引用数 (Scopus)

An 80 Gb/s optical I/O interface ATM switch MCM

Kawano, R., Yamanaka, N., Oki, E., Okazaki, K. & Ohki, A., 2002, In: Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi). 85, 2, p. 61-68 8 p.

研究成果: Article › 査読

An 80-Gbitls ATM Switch MCM

Okazaki, K., Sugiura, N., Harada, A., Kishimoto, T., Oki, E. & Yamanaka, N., 2002, In: journal of the japan institute of electronics packaging. 2, 7, p. 556-560 5 p.

研究成果: Article › 査読

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