0.5μm BiCMOS standard-cell macros including 0.5W 3ns register file and 0.6W 5ns 32kB cache

Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Shin'ichi Kobayashi, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Tadahiro Kuroda, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5μm BiCMOs technology. These power consumption values are at 100 MHz operation. Low power and high speed are crucial for high-performance systems requiring a high level of integration. Several BiCMOS/CMOS circuits achieve high-speed operation with a 3.3-V supply. A direct-coupled ECL (emitter-coupled logic)+CMOS circuit is investigated for use as a BiCMOS standard cell.

本文言語English
ホスト出版物のタイトルDigest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
出版社Institute of Electrical and Electronics Engineers Inc.
ページ46-47
ページ数2
ISBN(電子版)0780305736
DOI
出版ステータスPublished - 1992
外部発表はい
イベント39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States
継続期間: 1992 2月 191992 2月 21

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
1992-February
ISSN(印刷版)0193-6530

Conference

Conference39th IEEE International Solid-State Circuits Conference, ISSCC 1992
国/地域United States
CitySan Francisco
Period92/2/1992/2/21

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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