10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and V th tunability through thin BOX

Masumi Saitoh, Kensuke Ota, Chika Tanaka, Ken Uchida, Toshinori Numata

    研究成果: Conference contribution

    28 被引用数 (Scopus)

    抄録

    We demonstrate high-performance 10nm-diameter tri-gate nanowire transistors (NW Tr.) with V th tunability, small variability and negligible self-heating. Optimized S/D and stress memorization technique (SMT) lead to significant parasitic resistance reduction and mobility enhancement. Saturation velocity increase by SMT further enhances high-field carrier velocity and I on of 1mA/μm at I off of 100nA/μm is achieved. We also demonstrate V th control in tri-gate NW Tr. with thin BOX for the first time. The degradation of body effect by NW narrowing can be recovered by thinning NW height, enabling dynamic power and performance management.

    本文言語English
    ホスト出版物のタイトル2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
    ページ11-12
    ページ数2
    DOI
    出版ステータスPublished - 2012 9 27
    イベント2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
    継続期間: 2012 6 122012 6 14

    出版物シリーズ

    名前Digest of Technical Papers - Symposium on VLSI Technology
    ISSN(印刷版)0743-1562

    Other

    Other2012 Symposium on VLSI Technology, VLSIT 2012
    国/地域United States
    CityHonolulu, HI
    Period12/6/1212/6/14

    ASJC Scopus subject areas

    • 電子工学および電気工学

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