We demonstrate high-performance 10nm-diameter tri-gate nanowire transistors (NW Tr.) with V th tunability, small variability and negligible self-heating. Optimized S/D and stress memorization technique (SMT) lead to significant parasitic resistance reduction and mobility enhancement. Saturation velocity increase by SMT further enhances high-field carrier velocity and I on of 1mA/μm at I off of 100nA/μm is achieved. We also demonstrate V th control in tri-gate NW Tr. with thin BOX for the first time. The degradation of body effect by NW narrowing can be recovered by thinning NW height, enabling dynamic power and performance management.