1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

Kouichi Kanda, Danardono Dwi Antono, Koichi Ishida, Hiroshi Kawaguchi, Tadahiro Kuroda, Takayasu Sakurai

    研究成果: Conference article査読

    101 被引用数 (Scopus)

    抄録

    A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm2. The interface utilizes capacitively coupled contactless minipads, return-to-half-VDD signaling and sense amplifying F/F. The measured test chip fabricated in 0.35μm CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.

    本文言語English
    ページ(範囲)173+186-187+487
    ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    出版ステータスPublished - 2003 7 23
    イベント2003 Digest of Technical Papers - , United States
    継続期間: 2003 2 92003 2 13

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

    引用スタイル