1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

Tadahiro Kuroda, Tetsuya Fujita, Yasushi Itabashi, Satohiko Kabumoto, Makoto Noda, Akira Kanuma

研究成果: Conference article査読

9 被引用数 (Scopus)

抄録

The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 μm, 15 GHz bipolar process operate with a -2 V single power supply and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply. Gate stacking in ECL is effective in reducing power dissipation because complex logic can be implemented in a single gate with fewer current sources.

本文言語English
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
38
出版ステータスPublished - 1995 2 1
外部発表はい
イベントProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
継続期間: 1995 2 151995 2 17

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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