The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 μm, 15 GHz bipolar process operate with a -2 V single power supply and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply. Gate stacking in ECL is effective in reducing power dissipation because complex logic can be implemented in a single gate with fewer current sources.
|ジャーナル||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|出版ステータス||Published - 1995 2 1|
|イベント||Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA|
継続期間: 1995 2 15 → 1995 2 17
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering