3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link

Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

    研究成果: Article査読

    22 被引用数 (Scopus)

    抄録

    This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2 /Gbps, respectively, which are the same as those of two-chip integration.

    本文言語English
    論文番号5437487
    ページ(範囲)856-862
    ページ数7
    ジャーナルIEEE Journal of Solid-State Circuits
    45
    4
    DOI
    出版ステータスPublished - 2010 4

    ASJC Scopus subject areas

    • 電子工学および電気工学

    フィンガープリント

    「3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル