3D clock distribution using vertically/horizontally-coupled resonators

Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

    研究成果: Conference contribution

    8 被引用数 (Scopus)

    抄録

    Clock distribution with low skew, low jitter, and low power for high-performance microprocessors is a significant design challenge. Although traditional H-tree clock distribution circuits are widely used, the clock skew of such circuits is increased by the PVT variations associated with device scaling [1]. In recent years, there has thus been a growing interest in resonant clock distribution schemes for reduced clock skew. In particular, coupled ring oscillators with shorted outputs [2] can reduce skew and jitter without additional layout area compared to LC resonators [3]. The difference in phase and frequency of each oscillator (due to PVT variations) is equalized by the mutual connection between the oscillators. Power dissipation can also be reduced, as the enhanced variability tolerance may permit operation at lower voltages.

    本文言語English
    ホスト出版物のタイトル2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
    ページ258-259
    ページ数2
    DOI
    出版ステータスPublished - 2013 4 29
    イベント2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
    継続期間: 2013 2 172013 2 21

    出版物シリーズ

    名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
    56
    ISSN(印刷版)0193-6530

    Other

    Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
    国/地域United States
    CitySan Francisco, CA
    Period13/2/1713/2/21

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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