3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links

Kenichi Osada, Makoto Saen, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

研究成果: Conference contribution

15 引用 (Scopus)

抄録

This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an "open-skipped-inductor scheme" is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.

元の言語English
ホスト出版物のタイトルIEEE Symposium on VLSI Circuits, Digest of Technical Papers
ページ256-257
ページ数2
出版物ステータスPublished - 2009
イベント2009 Symposium on VLSI Circuits - Kyoto, Japan
継続期間: 2009 6 162009 6 18

Other

Other2009 Symposium on VLSI Circuits
Japan
Kyoto
期間09/6/1609/6/18

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Static random access storage
Electric power utilization
Demonstrations
Wire
Data storage equipment
Degradation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

これを引用

Osada, K., Saen, M., Okuma, Y., Niitsu, K., Shimazaki, Y., Sugimori, Y., ... Kuroda, T. (2009). 3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links. : IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 256-257). [5205351]

3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links. / Osada, Kenichi; Saen, Makoto; Okuma, Yasuyuki; Niitsu, Kiichi; Shimazaki, Yasuhisa; Sugimori, Yasufumi; Kohama, Yoshinori; Kasuga, Kazutaka; Nonomura, Itaru; Irie, Naohiko; Hattori, Toshihiro; Hasegawa, Atsushi; Kuroda, Tadahiro.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. p. 256-257 5205351.

研究成果: Conference contribution

Osada, K, Saen, M, Okuma, Y, Niitsu, K, Shimazaki, Y, Sugimori, Y, Kohama, Y, Kasuga, K, Nonomura, I, Irie, N, Hattori, T, Hasegawa, A & Kuroda, T 2009, 3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links. : IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 5205351, pp. 256-257, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.
Osada K, Saen M, Okuma Y, Niitsu K, Shimazaki Y, Sugimori Y その他. 3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links. : IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. p. 256-257. 5205351
Osada, Kenichi ; Saen, Makoto ; Okuma, Yasuyuki ; Niitsu, Kiichi ; Shimazaki, Yasuhisa ; Sugimori, Yasufumi ; Kohama, Yoshinori ; Kasuga, Kazutaka ; Nonomura, Itaru ; Irie, Naohiko ; Hattori, Toshihiro ; Hasegawa, Atsushi ; Kuroda, Tadahiro. / 3D System integration of processor and multi-stacked SRAMs by using inductive-coupling links. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. pp. 256-257
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AU - Shimazaki, Yasuhisa

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AU - Kohama, Yoshinori

AU - Kasuga, Kazutaka

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AB - This paper describes a three-dimensional (3D) system integration of a fully functional processor chip and two memory chips by using inductive coupling. To attain a shorter link distance for a smaller area and lower power consumption, a new 3D-integrated wire-penetrated multi-layer structure is developed. In addition, to prevent signal degradation due to unused inductors, an "open-skipped-inductor scheme" is proposed. We present the first demonstration that three fabricated chips are successfully AC-coupled by the inductive coupling. The power and area efficiency of the link are 1 pJ/b and 0.15 mm2/Gbps, respectively, which are the same as those of two-chip integration.

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