47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

研究成果: Article

8 引用 (Scopus)

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This paper presents a power reduction scheme and an area reduction scheme in inductive-coupling programmable bus for NAND flash memory stacking. A channel arrangement scheme using three coils enables random access for memory read and memory write. Transmit power is reduced by 47% compared to a previous design with shields. A coil layout style, herein noted as XY coil, allows for the coils to interleave with logic interconnections, resulting in area reduction of 91% relative to at the expense of only 17% transmit power increase. Relayed data transmission at 1.6 Gb/s and BER < 10-12 is achieved.

元の言語English
記事番号5582165
ページ(範囲)2269-2278
ページ数10
ジャーナルIEEE Transactions on Circuits and Systems I: Regular Papers
57
発行部数9
DOI
出版物ステータスPublished - 2010 9 24

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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