47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

    研究成果: Conference contribution

    7 被引用数 (Scopus)

    抄録

    An inductive-coupling programmable bus is developed for NAND flash memory access in Solid State Drive (SSD). A channel arrangement scheme using 3 coils enables random access for memory read and memory write. Transmission power is reduced by 47% compared to a previous design with 2 coils and a shield [1]. A coil layout style, namely XY coil, allows the coils covered by logic interconnections, resulting in area reduction by 91%. Relayed data transmission at 1.6Gb/s and BER<10-12 is achieved.

    本文言語English
    ホスト出版物のタイトル2009 IEEE Custom Integrated Circuits Conference, CICC '09
    ページ449-452
    ページ数4
    DOI
    出版ステータスPublished - 2009 12 1
    イベント2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
    継続期間: 2009 9 132009 9 16

    出版物シリーズ

    名前Proceedings of the Custom Integrated Circuits Conference
    ISSN(印刷版)0886-5930

    Other

    Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
    CountryUnited States
    CitySan Jose, CA
    Period09/9/1309/9/16

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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