50% active-power saving without speed degradation using standby power reduction (SPR) circuit

Katsuhiro Seta, Hiroyuki Hara, Tadahiro Kuroda, Masakazu Kakumu, Takayasu Sakurai

研究成果: Conference article査読

53 被引用数 (Scopus)

抄録

To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.

本文言語English
ページ(範囲)318-319
ページ数2
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
38
出版ステータスPublished - 1995 2月 1
外部発表はい
イベントProceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
継続期間: 1995 2月 151995 2月 17

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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