To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.
|ジャーナル||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|出版ステータス||Published - 1995 2月 1|
|イベント||Proceedings of the 1995 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA|
継続期間: 1995 2月 15 → 1995 2月 17
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