@inproceedings{d17f723040bd44bcac862f20dd1059bb,
title = "51k-gate low power ECL gate array family with metal-compiled and embedded SRAM",
abstract = "A family of 80ps, 1mW/gate series-gated ECL gate arrays of up to 51k-gate density is described. The family supports both metal-compiled SRAM with a TAA of 2.0ns. Raw core densities of 1125 gates/mm2 are achieved using a true ocean-of-cells, channel-less architecture. The arrays are fabricated using the ASSET-1 (All Spacer-Separated Element Transistor) 2-poly, 3-layer metal process with a conservative 1.2um emitter lithography.",
author = "D. Gray and D. Beeson and G. Daves and D. Hutchings and P. Thai and Wong, {T. S.} and T. Kuroda and M. Nakamura and M. Noda",
year = "1993",
month = jan,
day = "1",
language = "English",
isbn = "0780308263",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "Publ by IEEE",
pages = "23.4.1--23.4.4",
booktitle = "Proceedings of the Custom Integrated Circuits Conference",
note = "Proceedings of the IEEE 1993 Custom Integrated Circuits Conference ; Conference date: 09-05-1993 Through 12-05-1993",
}