60% power reduction in inductive-coupling inter-chip link by current-sensing technique

Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Hiroki Ishikuro, Tadahiro Kuroda

研究成果: Article査読

9 被引用数 (Scopus)

抄録

The demand for low-power and high-speed chip-to-chip communication between stacked chips in a system in a package (SiP) is increasing day by day. We have proposed and investigated a novel current-sensing technique in an inductive-coupling interchip link. Our current-sensing technique reduces total power dissipation by 60% compared with the conventional voltage-sensing technique without sacrificing either data rate (1 Gbit/s per channel) or bit error rate (<10-12). Additionally, the voltage-sensing technique and the current-sensing technique are compared from the viewpoint of circuit topology and the immunity to device mismatch. From a circuit simulation, the current-sensing technique was shown to have higher immunity to device mismatch and can reduce the transmitter power compared with voltage-sensing technique. We have reached a conclusion that the current-sensing technique is very effective for low-power operation in an inductive-coupling inter-chip link.

本文言語English
ページ(範囲)2215-2219
ページ数5
ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
46
4 B
DOI
出版ステータスPublished - 2007 4 24

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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