7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

本文言語English
ホスト出版物のタイトル2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(印刷版)9781479933273
DOI
出版ステータスPublished - 2014 1 1
イベント28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States
継続期間: 2014 6 102014 6 13

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other28th IEEE Symposium on VLSI Circuits, VLSIC 2014
国/地域United States
CityHonolulu, HI
Period14/6/1014/6/13

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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