7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Koichiro Masuyama; Yu Fujita; Hayate Okuhara; Hideharu Amano

doi:10.1109/FPL.2015.7293964

7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano

情報工学科

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Cool Mega Array (CMA)-SOTB-2 is an ultra-low energy Coarse Grained Reconfigurable Architecture[1] (CGRA) for recent advanced sensor networks, Internet of Things and wearable computing. It has a large Processing Element (PE) array without memory elements for mapping an application's data-flow graph, a small simple programmable μ-controller for data management, and data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. It is implemented by using Silicon on Thin BOX (SOTB) CMOS, a new process technology developed by the Low-power Electronics Association & Project (LEAP).

本文言語	English
ホスト出版物のタイトル	25th International Conference on Field Programmable Logic and Applications, FPL 2015
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（印刷版）	9780993428005
DOI	https://doi.org/10.1109/FPL.2015.7293964
出版ステータス	Published - 2015 10月 7
イベント	25th International Conference on Field Programmable Logic and Applications, FPL 2015 - London, United Kingdom 継続期間: 2015 9月 2 → 2015 9月 4

Other

Other	25th International Conference on Field Programmable Logic and Applications, FPL 2015
国/地域	United Kingdom
City	London
Period	15/9/2 → 15/9/4

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
信号処理
ソフトウェア
コンピュータサイエンスの応用

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引用スタイル

Masuyama, K, Fujita, Y, Okuhara, H & Amano, H 2015, 7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. in 25th International Conference on Field Programmable Logic and Applications, FPL 2015., 7293964, Institute of Electrical and Electronics Engineers Inc., 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, 15/9/2. https://doi.org/10.1109/FPL.2015.7293964

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title = "7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2",

abstract = "Cool Mega Array (CMA)-SOTB-2 is an ultra-low energy Coarse Grained Reconfigurable Architecture[1] (CGRA) for recent advanced sensor networks, Internet of Things and wearable computing. It has a large Processing Element (PE) array without memory elements for mapping an application's data-flow graph, a small simple programmable μ-controller for data management, and data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware context switching, storing intermediate data in registers, and clock distribution for them are eliminated from PE array which occupies large area of a chip. It is implemented by using Silicon on Thin BOX (SOTB) CMOS, a new process technology developed by the Low-power Electronics Association & Project (LEAP).",

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PY - 2015/10/7

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7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2

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Other

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