### 抄録

In this work, we propose an adder for the 2-Dimensional Nearest-Neighbor, Two-Qubit gate, Concurrent (2D NTC) architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the layout of logical qubits in two dimensions with (Mathematical Equation Presented) columns where each column has (Mathematical Equation Presented) qubits and the concurrent execution of one- and two-qubit gates with nearest-neighbor interaction only. The proposed adder works in three phases. In the first phase, the first column generates the summation output and the other columns do the carry-lookahead operations. In the second phase, these intermediate values are propagated from column to column, preparing for computation of the final carry for each register position. In the last phase, each column, except the first one, generates the summation output using this column-level carry. The depth and the number of qubits of the proposed adder are Θ(Mathematical Equation Presented) and O(n), respectively. The proposed adder executes faster than the adders designed for the 1D NTC architecture when the length of the input registers n is larger than 51.

元の言語 | English |
---|---|

記事番号 | 24 |

ジャーナル | ACM Journal on Emerging Technologies in Computing Systems |

巻 | 8 |

発行部数 | 3 |

DOI | |

出版物ステータス | Published - 2012 8 |

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### ASJC Scopus subject areas

- Hardware and Architecture
- Software
- Electrical and Electronic Engineering

### これを引用

**A Θ(Mathematical Equation Presented)-depth quantum adder on the 2D NTC quantum computer architecture.** / Choi, Byung Soo; Van Meter, Rodney D.

研究成果: Article

}

TY - JOUR

T1 - A Θ(Mathematical Equation Presented)-depth quantum adder on the 2D NTC quantum computer architecture

AU - Choi, Byung Soo

AU - Van Meter, Rodney D

PY - 2012/8

Y1 - 2012/8

N2 - In this work, we propose an adder for the 2-Dimensional Nearest-Neighbor, Two-Qubit gate, Concurrent (2D NTC) architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the layout of logical qubits in two dimensions with (Mathematical Equation Presented) columns where each column has (Mathematical Equation Presented) qubits and the concurrent execution of one- and two-qubit gates with nearest-neighbor interaction only. The proposed adder works in three phases. In the first phase, the first column generates the summation output and the other columns do the carry-lookahead operations. In the second phase, these intermediate values are propagated from column to column, preparing for computation of the final carry for each register position. In the last phase, each column, except the first one, generates the summation output using this column-level carry. The depth and the number of qubits of the proposed adder are Θ(Mathematical Equation Presented) and O(n), respectively. The proposed adder executes faster than the adders designed for the 1D NTC architecture when the length of the input registers n is larger than 51.

AB - In this work, we propose an adder for the 2-Dimensional Nearest-Neighbor, Two-Qubit gate, Concurrent (2D NTC) architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the layout of logical qubits in two dimensions with (Mathematical Equation Presented) columns where each column has (Mathematical Equation Presented) qubits and the concurrent execution of one- and two-qubit gates with nearest-neighbor interaction only. The proposed adder works in three phases. In the first phase, the first column generates the summation output and the other columns do the carry-lookahead operations. In the second phase, these intermediate values are propagated from column to column, preparing for computation of the final carry for each register position. In the last phase, each column, except the first one, generates the summation output using this column-level carry. The depth and the number of qubits of the proposed adder are Θ(Mathematical Equation Presented) and O(n), respectively. The proposed adder executes faster than the adders designed for the 1D NTC architecture when the length of the input registers n is larger than 51.

KW - 2D NTC quantum computer architecture

KW - Quantum adder

KW - Quantum arithmetic algorithms

KW - Quantum circuit

KW - Quantum computer

UR - http://www.scopus.com/inward/record.url?scp=84866100713&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866100713&partnerID=8YFLogxK

U2 - 10.1145/2287696.2287707

DO - 10.1145/2287696.2287707

M3 - Article

AN - SCOPUS:84866100713

VL - 8

JO - ACM Journal on Emerging Technologies in Computing Systems

JF - ACM Journal on Emerging Technologies in Computing Systems

SN - 1550-4832

IS - 3

M1 - 24

ER -