A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2V supply was designed and fabricated in 0.11 μm CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10-12 up to 32 Gb/s at a toggle rate of 8 GHz.
|出版ステータス||Published - 2004 9月 29|
|イベント||2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI - Honolulu, HI, United States|
継続期間: 2004 6月 17 → 2004 6月 19
|Other||2004 Symposium on VLSI Circuits, Digest of Technical Papers, 2004 VLSI|
|Period||04/6/17 → 04/6/19|
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