A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC

Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.

    本文言語English
    ホスト出版物のタイトル2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    ページ111-112
    ページ数2
    DOI
    出版ステータスPublished - 2013 5 20
    イベント2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan
    継続期間: 2013 1 222013 1 25

    出版物シリーズ

    名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    Other

    Other2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    CountryJapan
    CityYokohama
    Period13/1/2213/1/25

    ASJC Scopus subject areas

    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering

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