TY - GEN
T1 - A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC
AU - Yoshioka, Kentaro
AU - Shikata, Akira
AU - Sekimoto, Ryota
AU - Kuroda, Tadahiro
AU - Ishikuro, Hiroki
PY - 2013/5/20
Y1 - 2013/5/20
N2 - An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.
AB - An extremely low-voltage operating high speed and low power 2bit/step asynchronous SAR ADC is presented. Wide range dynamic threshold configuring comparator is proposed to enable power and area efficient 2bit/step operation. By configuring the comparator threshold by simple Vcm biased current sources, the ADC holds immunity against 10% power supply variation. The prototype ADC fabricated in 40nm CMOS achieved 44.3 dB SNDR with 6.14 MS/s at a single supply voltage of 0.5 V. The ADC achieved a peak FoM of 5.9fJ/conv-step at 0.4V and operates down to 0.35V.
UR - http://www.scopus.com/inward/record.url?scp=84877781428&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84877781428&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2013.6509581
DO - 10.1109/ASPDAC.2013.6509581
M3 - Conference contribution
AN - SCOPUS:84877781428
SN - 9781467330299
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 111
EP - 112
BT - 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
T2 - 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
Y2 - 22 January 2013 through 25 January 2013
ER -