A 0.5 v 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS

Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

研究成果: Article査読

90 被引用数 (Scopus)

抄録

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160 μm × 70 μm.

本文言語English
論文番号6165388
ページ(範囲)1022-1030
ページ数9
ジャーナルIEEE Journal of Solid-State Circuits
47
4
DOI
出版ステータスPublished - 2012 4月

ASJC Scopus subject areas

  • 電子工学および電気工学

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