@article{56de6e97fc36405fb7e08d860b4c978e,
title = "A 0.5 v 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS",
abstract = "This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160 μm × 70 μm.",
keywords = "ADC, CMOS, low-voltage, meta-stable, reconfigurable DAC, successive approximation, tri-level comparator",
author = "Akira Shikata and Ryota Sekimoto and Tadahiro Kuroda and Hiroki Ishikuro",
note = "Funding Information: Manuscript received August 27, 2011; revised November 23, 2011; accepted December 10, 2011. Date of publication March 06, 2012; date of current version March 28, 2012. This paper was approved by Guest Editor Makoto Nagata. This work was carried out as a part of the Extremely Low Power (ELP) project supported by METI and NEDO. This work was supported by Global COE Program “High-Level Global Cooperation for Leading-Edge Platform on Access Spaces (C12).” The authors are with Electrical Engineering Department, Keio University, Yokohama 223-8522, Japan (e-mail: shikata@iskr.elec.keio.ac.jp; sekimoto@ iskr.elec.keio.ac.jp; kuroda@ elec.keio.ac.jp; ishikuro@elec.keio.ac.jp). Copyright: Copyright 2012 Elsevier B.V., All rights reserved.",
year = "2012",
month = apr,
doi = "10.1109/JSSC.2012.2185352",
language = "English",
volume = "47",
pages = "1022--1030",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",
}