A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

    研究成果: Conference contribution

    39 被引用数 (Scopus)

    抄録

    This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

    本文言語English
    ホスト出版物のタイトル2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
    ページ262-263
    ページ数2
    出版ステータスPublished - 2011 9 16
    イベント2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
    継続期間: 2011 6 152011 6 17

    出版物シリーズ

    名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

    Other

    Other2011 Symposium on VLSI Circuits, VLSIC 2011
    国/地域Japan
    CityKyoto
    Period11/6/1511/6/17

    ASJC Scopus subject areas

    • 電子材料、光学材料、および磁性材料
    • 電子工学および電気工学

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