A 0.5V 6-bit scalable phase interpolator

Satoshi Kumaki, Abul Hasan Johari, Takeshi Matsubara, Isamu Hayashi, Hiroki Ishikuro

    研究成果: Conference contribution

    21 被引用数 (Scopus)

    抄録

    This paper proposes a scalable phase interpolator (PI) with dual-input inverter. A pseudo-pipelined architecture is proposed to realize resolution scalability and to reduce the circuit size and power consumption. By using a simple architecture, the proposed circuit operates at 0.5V at which conventional analog PI cannot operate. Slew rate of inverter chain is controlled by current starving technique to support phase interpolation at wide input frequency range. The PI was designed in 65nm-CMOS technology. The circuit simulation confirms 6-bit phase resolution, DNL of 0.41 LSB, and INL of 1.25 LSB. The power consumption is 0.12 μW/MHz.

    本文言語English
    ホスト出版物のタイトルProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
    ページ1019-1022
    ページ数4
    DOI
    出版ステータスPublished - 2010 12月 1
    イベント2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
    継続期間: 2010 12月 62010 12月 9

    出版物シリーズ

    名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

    Other

    Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
    国/地域Malaysia
    CityKuala Lumpur
    Period10/12/610/12/9

    ASJC Scopus subject areas

    • 電子工学および電気工学

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