A 0.5V 65nm-CMOS single phase clocked bootstrapped switch with rise time accelerator

Akira Shikata, Ryota Sekimoto, Hiroki Ishikuro

    研究成果: Conference contribution

    9 被引用数 (Scopus)

    抄録

    This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS process and the simulation results show that the power consumption of quasi differential bootstrapped switch is less than 11nW/MHz at a supply voltage of 0.5V with 10MS/sec. The third order harmonic distortion (HD3) is 104dB with sampling capacitor of 1.28pF.

    本文言語English
    ホスト出版物のタイトルProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
    ページ1015-1018
    ページ数4
    DOI
    出版ステータスPublished - 2010 12 1
    イベント2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
    継続期間: 2010 12 62010 12 9

    出版物シリーズ

    名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

    Other

    Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
    国/地域Malaysia
    CityKuala Lumpur
    Period10/12/610/12/9

    ASJC Scopus subject areas

    • 電子工学および電気工学

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