A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

研究成果: Article査読

313 被引用数 (Scopus)

抄録

A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD -Vth, design space is also studied.

本文言語English
ページ(範囲)1770-1777
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
31
11
出版ステータスPublished - 1996 11 1
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル