A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

研究成果: Chapter

抄録

A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a O.3-μ.m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD-Vth design space is also studied.

本文言語English
ホスト出版物のタイトルLow-Power CMOS Design
出版社John Wiley and Sons Inc.
ページ97-104
ページ数8
ISBN(電子版)9780470545058
ISBN(印刷版)9780780334298
DOI
出版ステータスPublished - 1998 1 1
外部発表はい

ASJC Scopus subject areas

  • 工学(全般)
  • コンピュータ サイエンス(全般)
  • エネルギー(全般)

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