1 TB/s 1 pJ/b 6.4 mm 2/TB/s inductive-coupling interface between 65-nm complementary metal-oxide-semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <10 -16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 ×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.
|ジャーナル||IEEE Journal on Emerging and Selected Topics in Circuits and Systems|
|出版ステータス||Published - 2012|
ASJC Scopus subject areas
- Electrical and Electronic Engineering