A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 μm in a layout area of 1 mm 2. The total layout area including 16 clock transceivers is 2 mm 2 in 0.18 μm CMOS and the chip thickness is reduced to 10 μm. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10 -13.
|ジャーナル||IEEE Journal of Solid-State Circuits|
|出版ステータス||Published - 2007 1月|
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