A 10-bit 80-MS/s decision-select successive approximation TDC in 65-nm CMOS

Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda

研究成果: Article査読

46 被引用数 (Scopus)

抄録

This paper presents a 10-bit 80-MS/s successive approximation time-to-digital converter (TDC) with a decision-select structure for on-chip timing measurement applications. Time-domain successive approximation is realized utilizing a relative timing difference between input and reference timings. While the successive approximation scheme allows high bit resolutions and low power consumptions, the decision-select structure enables fast bit conversions that lead to high sampling rates. The decision-select structure unrolls the successive approximation iteration loop and removes time-consuming timing estimation and adjustment procedures to minimize bit conversion times. As the successive approximation scheme relies on a binary search, exponential delay lines are adopted to achieve good power and noise performances by reducing the total number of delay stages. The proposed TDC uses only 0.048 delay stages per bit conversion. A test-chip prototype fabricated in a 65-nm CMOS technology consumes 9.6 mW at 80-MS/s and demonstrates 0.23-pJ/conversion-step figure-of merit (FOM) and 0.5-LSB single-shot precision.

本文言語English
論文番号6151852
ページ(範囲)1232-1241
ページ数10
ジャーナルIEEE Journal of Solid-State Circuits
47
5
DOI
出版ステータスPublished - 2012 5

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「A 10-bit 80-MS/s decision-select successive approximation TDC in 65-nm CMOS」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル